DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 538

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

1–94
Figure 1–83. MSByte and LSByte of the Two-Byte Transmitter Data Straddled Across Two Word Boundaries
Figure 1–84. MSByte and LSByte of the Four-Byte Transmitter Data Straddled Across Two Word Boundaries
Stratix IV Device Handbook Volume 2: Transceivers
tx_datain[15:8]
tx_datain[7:0]
(MSByte)
(LSByte)
tx_datain[31:16]
tx_datain[15:0]
(MSBytes)
(LSBytes)
D2
D1
D3D4
D1D2
In double-width modes with the 32-bit or 40-bit FPGA fabric-transceiver interface, the
byte deserializer receives two data bytes (16 or 20 bits) and deserializes it into four
data bytes (32 or 40 bits).
LSBytes of the four-byte transmitter data appears straddled across two word
boundaries after getting byte deserialized at the receiver.
Stratix IV GX and GT transceivers have an optional byte ordering block in the receiver
datapath that you can use to restore proper byte ordering before forwarding the data
to the FPGA fabric. The byte ordering block looks for the user-programmed byte
ordering pattern in the byte-deserialized data. You must select a byte ordering pattern
that you know appears at the LSByte(s) position of the parallel transmitter data. If the
byte ordering block finds the programmed byte ordering pattern in the MSByte(s)
position of the byte-deserialized data, it inserts the appropriate number of
user-programmed PAD bytes to push the byte ordering pattern to the LSByte(s)
position, thereby restoring proper byte ordering.
D4
D3
Transmitter
D7D8
D5D6
Transmitter
D6
D5
Serializer
Serializer
Byte
Byte
xx D1D2 D2D4 D5D6 D7D8 xx
xx D1 D2 D3 D4 D5 D6 xx
Figure 1–84
shows a scenario in which the two MSBytes and
Deserializer
Deserializer
Byte
Chapter 1: Transceiver Architecture in Stratix IV Devices
Byte
Receiver
Receiver
D1
xx
D1D2
xx
D3
D2
D5D6
D3D4
February 2011 Altera Corporation
D5
D4
Transceiver Block Architecture
D7D8
xx
D6
xx
rx_dataout[31:16]
rx_dataout[15:0]
(LSBytes)
(MSBytes)
rx_dataout[15:8]
rx_dataout[7:0]
(LSByte)
(MSByte)