DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 668
![KIT DEVELOPMENT STRATIX IV](/photos/28/41/284156/dk-dev-4sgx230n_sml.jpg)
DK-DEV-4SGX230N
Manufacturer Part Number
DK-DEV-4SGX230N
Description
KIT DEVELOPMENT STRATIX IV
Manufacturer
Altera
Series
Stratix® IVr
Type
FPGAr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.DK-DEV-4SGX230N.pdf
(2 pages)
4.DK-DEV-4SGX530N.pdf
(57 pages)
Specifications of DK-DEV-4SGX230N
Contents
Development Board, Universal Power Supply, Cables and Software
Silicon Manufacturer
Altera
Core Architecture
FPGA
Core Sub-architecture
Stratix
Silicon Core Number
EP4S
Silicon Family Name
Stratix IV GX
Rohs Compliant
Yes
For Use With/related Products
EP4SGX230K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-2594
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DK-DEV-4SGX230N
Manufacturer:
Altera
Quantity:
135
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- DK-DEV-4SGX230N PDF datasheet #3
- DK-DEV-4SGX530N PDF datasheet #4
- Current page: 668 of 1154
- Download datasheet (32Mb)
1–224
Table 1–78. Stratix IV GX and GT ALTGX Megafunction Ports: Reset and Power Down (Part 2 of 2)
Table 1–79. Stratix IV GX and GT ALTGX Megafunction Ports: Calibration Block
Reference Information
Stratix IV Device Handbook Volume 2: Transceivers
rx_analogreset
tx_digitalreset
cal_blk_clk
cal_blk_powerdown
Port Name
Port Name
Table 1–79
Use the links listed in
terms used in this chapter.
Table 1–80. Reference Information (Part 1 of 3)
Basic (PMA Direct) Functional Mode
Clock and Data Recovery Unit (CDR)
Auxiliary Transmit (ATX) PLL Block
Output
Output
(OIF) CEI PHY Interface Mode
Input/
Input/
Input
Input
Input
Input
Terms Used in this Chapter
CMU Channel Architecture
lists the ALTGX megafunction calibration block ports.
Built-In Self Test Modes
Basic Functional Mode
Byte Ordering Block
Calibration Blocks
8B/10B Decoder
8B/10B Encoder
Byte Serializer
CMU0 PLL
CMU1 PLL
Clock Domain
Asynchronous
Asynchronous
pulse width is
pulse width is
Clock Domain
clock cycles.
clock cycles.
two parallel
two parallel
AEQ
Clock signal
Clock signal
Minimum
Minimum
signal.
signal.
Table 1–80
Receiver PMA reset.
■
Transmitter PCS reset.
■
for more information about some useful reference
Clock for transceiver calibration blocks.
Calibration block power down control.
When asserted high—analog circuitry within the
receiver PMA gets reset. Refer to
Power Down.
When asserted high, the transmitter PCS blocks
are reset. Refer to
Chapter 1: Transceiver Architecture in Stratix IV Devices
Description
Reset Control and Power Down.
Description
Useful Reference Points
page 1–181
page 1–195
page 1–187
page 1–111
page 1–206
page 1–201
page 1–100
page 1–102
page 1–102
page 1–89
page 1–23
page 1–50
page 1–95
page 1–93
page 1–53
February 2011 Altera Corporation
Reset Control and
Reference Information
Channel
Channel
Scope
Scope
Device
Device
Related parts for DK-DEV-4SGX230N
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
![DK-DEV-2AGX125N](/photos/28/41/284154/dk-dev-2agx125n_tmb.jpg)
Part Number:
Description:
KIT DEV ARRIA II GX FPGA 2AGX125
Manufacturer:
Altera
Datasheet:
![DK-DEV-3CLS200N](/photos/9/24/92409/dk-dev-3cls200n_tmb.jpg)
Part Number:
Description:
KIT DEV CYCLONE III LS EP3CLS200
Manufacturer:
Altera
Datasheet:
![DK-DEV-4SE530N](/photos/28/41/284157/dk-dev-4se530n_tmb.jpg)
Part Number:
Description:
KIT DEV STRATIX IV FPGA 4SE530
Manufacturer:
Altera
Datasheet:
![DK-DEV-2AGX260N](/photos/28/41/284175/dk-dev-2agx260n_tmb.jpg)
Part Number:
Description:
KIT DEV FPGA 2AGX260 W/6.375G TX
Manufacturer:
Altera
Datasheet:
![DK-DEV-5M570ZN](/photos/18/31/183180/dk-dev-5m570zn_tmb.jpg)
Part Number:
Description:
KIT DEV MAX V 5M570Z
Manufacturer:
Altera
Datasheet:
![DK-DEV-5SGXEA7/ES](/images/manufacturer_photos/0/0/40/altera_tmb.jpg)
Part Number:
Description:
KIT DEV STRATIX V FPGA 5SGXEA7
Manufacturer:
Altera
Datasheet:
![DK-DEV-3SL150N](/photos/9/20/92079/dk-dev-3sl150n_tmb.jpg)
Part Number:
Description:
KIT DEVELOPMENT STRATIX III
Manufacturer:
Altera
Datasheet:
![DK-DEV-1AGX60N](/photos/9/31/93181/mfgdk-dev-1agx60n_tmb.jpg)
Part Number:
Description:
KIT DEV ARRIA GX 1AGX60N
Manufacturer:
Altera
Datasheet:
![DK-DEV-4CGX150N](/images/manufacturer_photos/0/0/40/altera_tmb.jpg)
Part Number:
Description:
KIT STARTER CYCLONE IV GX
Manufacturer:
Altera
Datasheet:
![DK-DEV-4SGX530N](/images/manufacturer_photos/0/0/40/altera_tmb.jpg)
Part Number:
Description:
KIT DEVELOPMENT STRATIX IV
Manufacturer:
Altera
Datasheet:
![EP610PC-35](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 35 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
![EP610PC-15](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 15 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet: