DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 163

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

Chapter 5: Clock Networks and PLLs in Stratix IV Devices
PLLs in Stratix IV Devices
February 2011 Altera Corporation
The rselodd bit indicates an odd divide factor for the VCO output frequency along
with a 50% duty cycle. For example, if the post-scale divide factor is 3, the high- and
low-time count values could be set to 2 and 1, respectively, to achieve this division.
This implies a 67% - 33% duty cycle. If you need a 50% - 50% duty cycle, you can set
the rselodd control bit to 1 to achieve this duty cycle despite an odd division factor.
The PLL implements this duty cycle by transitioning the output clock from high to
low on a falling edge of the VCO output clock. When you set rselodd = 1, you
subtract 0.5 cycles from the high time and you add 0.5 cycles to the low time. For
example:
■
■
■
Scan Chain Description
The length of the scan chain varies for different Stratix IV PLLs. The top and bottom
PLLs have ten post-scale counters and a 234-bit scan chain, while the left and right
PLLs have seven post-scale counters and a 180-bit scan chain.
number of bits for each component of a Stratix IV PLL.
Table 5–11. Top and Bottom PLL Reprogramming Bits (Part 1 of 2)
Charge Pump Current
VCO Post-Scale divider (K)
High-time count = 2 cycles
Low-time count = 1 cycle
rselodd = 1 effectively equals:
■
■
■
High-time count = 1.5 cycles
Low-time count = 1.5 cycles
Duty cycle = (1.5/3) % high-time count and (1.5/3) % low-time count
Block Name
C9
C6
C8
C7
C5
C4
C3
C2
C1
C0
M
N
(2)
(3)
Counter
16
16
16
16
16
16
16
16
16
16
16
16
0
1
Number of Bits
Other
2
2
2
2
2
2
2
2
2
2
2
2
3
0
Stratix IV Device Handbook Volume 1
(1)
Table 5–11
Total
18
18
18
18
18
18
18
18
18
18
18
18
lists the
3
1
5–47