DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 573

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

Chapter 1: Transceiver Architecture in Stratix IV Devices
Transceiver Block Architecture
Figure 1–106. Stratix IV GX and GT Transceivers in PCIe Functional Mode
February 2011 Altera Corporation
(FPGA Fabric-Transceiver
(FPGA Fabric-Transceiver
Interface Clock Cycles)
Interface Clock Cycles)
Interface Frequency
PCS-FPGA Fabric
PCS-FPGA Fabric
TX PCS Latency
Interface Frequency
RX PCS Latency
Rate Match FIFO
PCS-hardIP or
8B/10B Encoder/
Functional Mode
Channel Bonding
Interface Width
PCS-hardIP or
Interface Width
Interface Width
Byte SerDes
PCI Express
Word Aligner
Data Rate
PMA-PCS
PMA-PCS
Functional
Decoder
(Pattern)
hardIP
Modes
Figure 1–106
PCIe functional mode.
8-bit
Single
Width
10-bit
Enabled
250 MHz
Disabled
20 - 24
8-Bit
5 - 6
Basic
16-bit
shows the Stratix IV GX and GT transceiver configurations allowed in
Double
Width
(/K28.5+/,/K28.5-/)
Synchronization
State Machine
Stratix IV GX and GT Configurations
2.5 Gbps
x1, x4, x8
Automatic
Enabled
Enabled
(Gen1)
20-bit
10-Bit
250 MHz
Disabled
20 - 24
5 - 6
8-Bit
PIPE
10-bit
Disabled
10-bit
XAUI
125 MHz
Enabled
4 - 5.5
16-Bit
11.5 -
14.5
GIGE
10-bit
PIPE
Protocol
SRIO
10-bit
SONET
Stratix IV Device Handbook Volume 2: Transceivers
/SDH
8-bit
Enabled
Disabled
500 MHz
20 - 24
8-Bit
5 - 6
16-bit
(OIF)
CEI
10-bit
(/K28.5+/,/K28.5-/)
SDI
Synchronization
State Machine
Automatic
x1, x4, x8
Enabled
Enabled
5 Gbps
(Gen2)
10-Bit
10-Bit
Deterministic
Latency
20-Bit
Disabled
250 MHz
Enabled
4 - 5.5
16-Bit
11.5 -
14.5
1–129