DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 91

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

Chapter 4: DSP Blocks in Stratix IV Devices
Stratix IV DSP Block Resource Descriptions
February 2011 Altera Corporation
A feature of the input register bank is to support a tap delay line. Therefore, the top
leg of the multiplier input (A) can be driven from general routing or from the cascade
chain, as shown in
signals.
Figure 4–7. Input Register of a Half DSP Block
At compile time, you must select whether the A-input comes from general routing or
from the cascade chain. In cascade mode, the dedicated shift outputs from one
multiplier block and directly feeds the input registers of the adjacent multiplier below
it (within the same half DSP block) or the first multiplier in the next half DSP block, to
form an 8-tap shift register chain per DSP Block. The DSP block can increase the
length of the shift register chain by cascading to the lower DSP blocks. The dedicated
shift register chain spans a single column, but you can implement longer shift register
chains requiring multiple columns using the regular FPGA routing resources.
datab_2[17..0]
dataa_3[17..0]
datab_3[17..0]
dataa_1[17..0]
datab_1[17..0]
dataa_2[17..0]
dataa_0[17..0]
datab_0[17..0]
loopback
scanina[17..0]
Figure
4–7.
clock[3..0]
Table 4–9 on page 4–34
ena[3..0]
aclr[3..0]
Register
Delay
scanouta
signa
signb
+/-
+/-
lists the DSP block dynamic
Stratix IV Device Handbook Volume 1
4–11