DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 307

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
Left and Right PLLs (PLL_Lx and PLL_Rx)
Figure 8–22. Phase Relationship for External PLL Interface Signals
Left and Right PLLs (PLL_Lx and PLL_Rx)
February 2011 Altera Corporation
(internal PLL clk)
phase shift)
phase shift)
phase shift)
Serial data
c0 (-180
VCO clk
c1 (288
c2 (-18
inclk0
f
D1
The
data are edge aligned. Introducing a phase shift of –180° to sampling clock (c0)
ensures that the input data is center-aligned with respect to the c0, as shown in
Figure
The Stratix IV device family contains up to eight left and right PLLs with up to four
PLLs located on the left side and four on the right side of the device. The left PLLs can
support high-speed differential I/O banks on the left side; the right PLLs can support
high-speed differential I/O banks on the right side of the device. The high-speed
differential I/O receiver and transmitter channels use these left and right PLLs to
generate the parallel clocks (rx_outclock and tx_outclock) and high-speed clocks
(diffioclk).
Figure 8–2 on page 8–3
right PLLs for Stratix IV E, GT, and GX devices. The PLL VCO operates at the clock
frequency of the data rate. Clock switchover and dynamic reconfiguration are allowed
using the left and right PLL in high-speed differential I/O support mode.
For more information, refer to the
Equation 8–1
8–22.
D2
D3
calculations for phase shift assume that the input clock and serial
and
D4
Figure 8–3 on page 8–4
D5
Clock Network and PLLs in Stratix IV Devices
D6
D7
show the locations of the left and
D8
Stratix IV Device Handbook Volume 1
D9
D10
chapter.
8–29