DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 540
![KIT DEVELOPMENT STRATIX IV](/photos/28/41/284156/dk-dev-4sgx230n_sml.jpg)
DK-DEV-4SGX230N
Manufacturer Part Number
DK-DEV-4SGX230N
Description
KIT DEVELOPMENT STRATIX IV
Manufacturer
Altera
Series
Stratix® IVr
Type
FPGAr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.DK-DEV-4SGX230N.pdf
(2 pages)
4.DK-DEV-4SGX530N.pdf
(57 pages)
Specifications of DK-DEV-4SGX230N
Contents
Development Board, Universal Power Supply, Cables and Software
Silicon Manufacturer
Altera
Core Architecture
FPGA
Core Sub-architecture
Stratix
Silicon Core Number
EP4S
Silicon Family Name
Stratix IV GX
Rohs Compliant
Yes
For Use With/related Products
EP4SGX230K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-2594
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DK-DEV-4SGX230N
Manufacturer:
Altera
Quantity:
135
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- DK-DEV-4SGX230N PDF datasheet #3
- DK-DEV-4SGX530N PDF datasheet #4
- Current page: 540 of 1154
- Download datasheet (32Mb)
1–96
Stratix IV Device Handbook Volume 2: Transceivers
1
Table 1–35
Table 1–35. Double Width Functional Modes for the Byte Ordering Block
For more information about configurations that allow the byte ordering block in the
receiver datapath, refer to
In Basic double-width modes, you can program a custom byte ordering pattern and
byte ordering PAD pattern in the ALTGX MegaWizard Plug-In Manager.
lists the byte ordering pattern length allowed in Basic double-width mode.
Table 1–36. Byte Ordering Pattern Length in Basic Double-Width Mode
Basic double-width mode with:
Basic double-width mode with:
Basic double-width mode with:
Basic double-width mode with:
■
■
■
Basic double-width mode with:
■
■
■
Basic double-width mode with:
■
■
■
Note to
(1) The 18-bit byte ordering pattern D[17:0] consists of MSByte D[17:9] and LSByte D[8:0]; D[17] corresponds
32-bit FPGA fabric-transceiver interface
No 8B/10B decoder (16-bit PMA-PCS interface)
Word aligner in manual alignment mode
32-bit FPGA fabric-transceiver interface
8B/10B decoder (20-bit PMA-PCS interface)
Word aligner in manual alignment mode
40-bit FPGA fabric-transceiver interface
No 8B/10B decoder (20-bit PMA-PCS interface)
Word aligner in manual alignment mode
Byte Ordering Block in Double-Width Modes
to rx_ctrldetect[1] and D[16:9] corresponds to rx_dataout[15:8]. Similarly, D[9] corresponds to
rx_ctrldetect[0] and D[7:0] corresponds to rx_dataout[7:0].
Table
Functional Modes
lists the double-width byte ordering block functional modes.
1–36:
Functional Mode
“Basic Double-Width Mode Configurations” on page
■
■
■
■
■
■
■
■
■
32-bit FPGA fabric-transceiver interface
No 8B/10B decoder (16-bit PMA-PCS interface)
Word aligner in manual alignment mode
32-bit FPGA fabric-transceiver interface
8B/10B decoder (20-bit PMA-PCS interface)
Word aligner in manual alignment mode
40-bit FPGA fabric-transceiver interface
No 8B/10B decoder (20-bit PMA-PCS interface)
Word aligner in manual alignment mode
Chapter 1: Transceiver Architecture in Stratix IV Devices
18 bits, 9 bits
Pattern Length
20 bits, 10 bits
Byte Ordering
16 bits, 8 bits
Descriptions
(1)
February 2011 Altera Corporation
Transceiver Block Architecture
Byte Ordering PAD
Pattern Length
10 bits
Table 1–36
8 bits
9 bits
1–117.
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