DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 748
![KIT DEVELOPMENT STRATIX IV](/photos/28/41/284156/dk-dev-4sgx230n_sml.jpg)
DK-DEV-4SGX230N
Manufacturer Part Number
DK-DEV-4SGX230N
Description
KIT DEVELOPMENT STRATIX IV
Manufacturer
Altera
Series
Stratix® IVr
Type
FPGAr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.DK-DEV-4SGX230N.pdf
(2 pages)
4.DK-DEV-4SGX530N.pdf
(57 pages)
Specifications of DK-DEV-4SGX230N
Contents
Development Board, Universal Power Supply, Cables and Software
Silicon Manufacturer
Altera
Core Architecture
FPGA
Core Sub-architecture
Stratix
Silicon Core Number
EP4S
Silicon Family Name
Stratix IV GX
Rohs Compliant
Yes
For Use With/related Products
EP4SGX230K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-2594
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DK-DEV-4SGX230N
Manufacturer:
Altera
Quantity:
135
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- DK-DEV-4SGX230N PDF datasheet #3
- DK-DEV-4SGX530N PDF datasheet #4
- Current page: 748 of 1154
- Download datasheet (32Mb)
2–76
Figure 2–39. Sixteen Identical Channels Across Four Transceiver Blocks for Configuration Example 2
Stratix IV Device Handbook Volume 2: Transceivers
Configuration Example 2: Configuring Sixteen Identical Channels Across
Four Transceiver Blocks
1
This example relates to
Clock” on page
Figure 2–39
blocks. The tx_coreclk ports of all 16 transmitter channels are connected together
and driven by the tx_clkout[4] signal from channel 0 in transceiver block GXBR1. The
tx_clkout[4] signal also drives the transmitter data and control logic of all 16
transmitter channels in the FPGA fabric. With this clocking scheme, only one global
clock resource is used by the tx_clkout[4] signal.
Channel [15:12]
Channel [11:8]
Channel [3:0]
Channel [7:4]
and Control
and Control
and Control
and Control
TX Data
shows 16 identical transmitter channels located across four transceiver
TX Data
TX Data
TX Data
FPGA
Fabric
Logic
Logic
Logic
Logic
2–69.
tx_coreclk[15:12]
tx_coreclk[7:4]
tx_coreclk[11:8]
tx_coreclk[3:0]
“User-Selected Receiver Phase Compensation FIFO Read
tx_clkout[12]
tx_clkout[4]
tx_clkout[8]
tx_clkout[0]
Transceiver Block GXBR3
Transceiver Block GXBR2
Transceiver Block GXBR0
Transceiver Block GXBR1
Chapter 2: Transceiver Clocking in Stratix IV Devices
Channel 3
Channel 2
Channel 1
Channel 0
Channel 3
Channel 2
Channel 1
Channel 0
Channel 3
Channel 2
Channel 1
Channel 0
Channel 3
Channel 2
Channel 1
Channel 0
February 2011 Altera Corporation
Configuration Examples
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