DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 1139
![KIT DEVELOPMENT STRATIX IV](/photos/28/41/284156/dk-dev-4sgx230n_sml.jpg)
DK-DEV-4SGX230N
Manufacturer Part Number
DK-DEV-4SGX230N
Description
KIT DEVELOPMENT STRATIX IV
Manufacturer
Altera
Series
Stratix® IVr
Type
FPGAr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.DK-DEV-4SGX230N.pdf
(2 pages)
4.DK-DEV-4SGX530N.pdf
(57 pages)
Specifications of DK-DEV-4SGX230N
Contents
Development Board, Universal Power Supply, Cables and Software
Silicon Manufacturer
Altera
Core Architecture
FPGA
Core Sub-architecture
Stratix
Silicon Core Number
EP4S
Silicon Family Name
Stratix IV GX
Rohs Compliant
Yes
For Use With/related Products
EP4SGX230K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-2594
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DK-DEV-4SGX230N
Manufacturer:
Altera
Quantity:
135
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- DK-DEV-4SGX230N PDF datasheet #3
- DK-DEV-4SGX530N PDF datasheet #4
- Current page: 1139 of 1154
- Download datasheet (32Mb)
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Switching Characteristics
Table 1–43. DPA Lock Time Specifications—Stratix IV GX and GT Devices Only
Figure 1–5. LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specification for a Data Rate Equal to or Higher Than
1.25 Gbps
April 2011 Altera Corporation
SPI-4
Parallel Rapid I/O
Miscellaneous
Notes to
(1) The DPA lock time is for one channel.
(2) One data transition is defined as a 0-to-1 or 1-to-0 transition.
(3) The DPA lock time stated in the table applies to both commercial and industrial grade.
(4) This is the number of repetitions for the stated training pattern to achieve the 256 data transitions.
Standard
Table
1–43:
0.35
8.5
25
0.1
F1
Table 1–43
Figure 1–5
a data rate equal to or higher than 1.25 Gbps.
form.
00000000001111111111
F2
Training Pattern
00001111
10010000
10101010
01010101
shows the LVDS soft-CDR/DPA sinusoidal jitter tolerance specification for
lists the DPA lock time specifications for Stratix IV GX and GT devices.
LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specification
Transitions in One
Repetition of the
Training Pattern
Number of Data
Jitter Frequency (Hz)
2
2
4
8
8
Stratix IV Device Handbook Volume 4: Device Datasheet and Addendum
F3
Table 1–44
per 256 Data Transitions
Number of Repetitions
(Note
128
128
64
32
32
(4)
1), (2),
lists this information in table
(3)
F4
640 data transitions
640 data transitions
640 data transitions
640 data transitions
640 data transitions
Maximum
1–57
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