DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 148

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

5–32
Figure 5–29. External Feedback Mode in Stratix IV Devices
Stratix IV Device Handbook Volume 1
Clock Multiplication and Division
inclk
Figure 5–28
clocks in external feedback mode.
Figure 5–28. Phase Relationship Between the PLL Clocks in External Feedback Mode
Note to
(1) The PLL clock outputs can lead or lag the fbin clock input.
Figure 5–29
Each Stratix IV PLL provides clock synthesis for PLL output ports using
M/(N* post-scale counter) scaling factors. The input clock is divided by a pre-scale
factor, n, and is then multiplied by the m feedback factor. The control loop drives the
VCO to match f
divides down the high-frequency VCO. For multiple PLL outputs with different
frequencies, the VCO is set to the least common multiple of the output frequencies
that meets its frequency specifications. For example, if the output frequencies required
from one PLL are 33 and 66 MHz, the Quartus II software sets the VCO to 660 MHz
(the least common multiple of 33 and 66 MHz within the VCO range). Then the
post-scale counters scale down the VCO frequency for each output port.
÷n
Figure
5–28:
shows an example waveform of the phase relationship between the PLL
shows external feedback mode implementation in Stratix IV devices.
fbin Clock Input Pin
Clock Outputs (1)
in
PFD
Dedicated PLL
PLL Reference
(M/N). Each output port has a unique post-scale counter that
Clock Port (1)
PLL Clock at
Clock at the
the Register
Input Pin
CP/LF
Phase Aligned
VCO
÷C0
÷C1
÷m
Chapter 5: Clock Networks and PLLs in Stratix IV Devices
fbout
fbin
PLL_<#>_CLKOUT#
PLL_<#>_CLKOUT#
February 2011 Altera Corporation
external
board
trace
PLLs in Stratix IV Devices