DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 828
![KIT DEVELOPMENT STRATIX IV](/photos/28/41/284156/dk-dev-4sgx230n_sml.jpg)
DK-DEV-4SGX230N
Manufacturer Part Number
DK-DEV-4SGX230N
Description
KIT DEVELOPMENT STRATIX IV
Manufacturer
Altera
Series
Stratix® IVr
Type
FPGAr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.DK-DEV-4SGX230N.pdf
(2 pages)
4.DK-DEV-4SGX530N.pdf
(57 pages)
Specifications of DK-DEV-4SGX230N
Contents
Development Board, Universal Power Supply, Cables and Software
Silicon Manufacturer
Altera
Core Architecture
FPGA
Core Sub-architecture
Stratix
Silicon Core Number
EP4S
Silicon Family Name
Stratix IV GX
Rohs Compliant
Yes
For Use With/related Products
EP4SGX230K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-2594
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DK-DEV-4SGX230N
Manufacturer:
Altera
Quantity:
135
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- DK-DEV-4SGX230N PDF datasheet #3
- DK-DEV-4SGX530N PDF datasheet #4
- Current page: 828 of 1154
- Download datasheet (32Mb)
4–22
Figure 4–12. Reset Sequence of PCIe Functional Mode
Notes to
(1) For t
(2) The minimum T1 and T2 period is 4 μs.
(3) The minimum T3 period is two parallel clock cycles.
Stratix IV Device Handbook Volume 2: Transceivers
Reset / Power Down Signals
Figure
pll_powerdown
PCIe Functional Mode
Output Status Signals
4–12:
duration, refer to the
pll _ powerdown
rx _ analogreset
rx _ pll _locked
rx _ freqlocked
tx _ digitalreset
rx _ digitalreset
pll _locked
You can configure PCIe functional mode with or without the receiver clock rate
compensation FIFO in the Stratix IV device. The reset sequence remains the same
whether or not you use the receiver clock rate compensation FIFO.
PCIe Reset Sequence
The PCIe protocol consists of an initialization/compliance phase and a normal
operation phase. The reset sequences for these two phases are described based on the
timing diagram in
busy
1
t
pll_powerdown (1)
DC and Switching Characteristics for Stratix IV Devices
Initialization / Compliance Phase
2
Figure
Two parallel clock cycles
4–12.
3
4
5
6
7
8
9
Chapter 4: Reset Control and Power Down in Stratix IV Devices
T1 (2)
chapter.
10
Normal Operation Phase
Ignore receive data
11
February 2011 Altera Corporation
T2 (2)
Transceiver Reset Sequences
12
T3 (3)
13
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