EP4CGX150CF23I7N Altera, EP4CGX150CF23I7N Datasheet - Page 95

• Manufacturer Part Number: EP4CGX150CF23I7N
• Description: IC CYCLONE IV FPGA 150K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV GXr

Specifications of EP4CGX150CF23I7N

• Number Of Logic Elements/cells: 149760
• Number Of Labs/clbs: 9360
• Total Ram Bits: 6480000
• Number Of I /o: 270
• Voltage - Supply: 1.16 V ~ 1.24 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 484-FBGA
• Family Name: Cyclone IV
• Number Of Logic Blocks/elements: 149760
• # I/os (max): 270
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 149760
• Ram Bits: 6635520
• Operating Supply Voltage (min): 1.16V
• Operating Supply Voltage (max): 1.24V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 5: Clock Networks and PLLs in Cyclone IV Devices
Phase Shift Implementation
© December 2010 Altera Corporation
Equation 5–1. Fine Resolution Phase Shift
Equation 5–1
in which f
For example, if f

depends on reference clock frequency and counter settings.
Coarse resolution phase shifts are implemented by delaying the start of the counters
for a predetermined number of counter clocks.
shift.
Equation 5–2. Coarse Resolution Phase Shift
C is the count value set for the counter delay time (this is the initial setting in the PLL
usage section of the compilation report in the Quartus II software). If the initial value
is 1, C – 1 = 0° phase shift.
Figure 5–21
VCO phase taps method. The eight phases from the VCO are shown and labeled for
reference. In this example, CLK0 is based on 0° phase from the VCO and has the C
value for the counter set to one. The CLK1 signal is divided by four, two VCO clocks
for high time and two VCO clocks for low time. CLK1 is based on the 135° phase tap
from the VCO and has the C value for the counter set to one. The CLK1 signal is also
divided by four. In this case, the two clocks are offset by 3 
0° phase from the VCO but has the C value for the counter set to three. This creates a
delay of two 
fine
= 156.25 ps. The PLL operating frequency defines this phase shift, a value that
REF
shows an example of phase shift insertion using fine resolution through
is the input reference clock frequency.
shows the minimum delay time that you can insert using this method.
coarse
REF
is 100 MHz, N = 1, and M = 8, then f
(two complete VCO periods).
 fine
 coarse
=
T
-----------
VCO
8
=
=
C 1
----------- -
f
VCO
------------- -
8f
–
VCO
1
=
Equation 5–2
=

-------------------- -
C 1
Mf
----------------- -
8Mf
–
REF
N
N
REF
VCO
Cyclone IV Device Handbook, Volume 1
= 800 MHz, and
fine
shows the coarse phase
. CLK2 is based on the
5–33