EP4CGX150CF23I7N Altera, EP4CGX150CF23I7N Datasheet - Page 371

• Manufacturer Part Number: EP4CGX150CF23I7N
• Description: IC CYCLONE IV FPGA 150K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV GXr

Specifications of EP4CGX150CF23I7N

• Number Of Logic Elements/cells: 149760
• Number Of Labs/clbs: 9360
• Total Ram Bits: 6480000
• Number Of I /o: 270
• Voltage - Supply: 1.16 V ~ 1.24 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 484-FBGA
• Family Name: Cyclone IV
• Number Of Logic Blocks/elements: 149760
• # I/os (max): 270
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 149760
• Ram Bits: 6635520
• Operating Supply Voltage (min): 1.16V
• Operating Supply Voltage (max): 1.24V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 2: Cyclone IV Reset Control and Power Down
Transceiver Reset Sequences
Figure 2–2. Transceiver Reset Sequences Chart
Notes to
(1) Refer to the Timing Diagram in
(2) Refer to the Timing Diagram in
(3) Refer to the Timing Diagram in
(4) Refer to the Timing Diagram in
(5) Refer to the Timing Diagram in
(6) Refer to the Timing Diagram in
(7) Refer to the Timing Diagram in
(8) Refer to the Timing Diagram in
All Supported Functional Modes Except the PCIe Functional Mode
© December 2010 Altera Corporation
reconfiguration mode
Reset Sequence
for PLL
Figure
Dynamic Reconfiguration
2–2:
1
reconfiguration mode
Reset Sequence
for channel
Figure 2–2
This section describes reset sequences for transceiver channels in bonded and
non-bonded configurations. Timing diagrams of some typical configurations are
shown to facilitate proper reset sequence implementation. In these functional modes,
you can set the receiver CDR either in automatic lock or manual lock mode.
In manual lock mode, the receiver CDR locks to the reference clock (lock-to-reference)
or the incoming serial data (lock-to-data), depending on the logic levels on the
rx_locktorefclk and rx_locktodata signals. With the receiver CDR in manual
lock mode, you can either configure the transceiver channels in the Cyclone IV GX
device in a non-bonded configuration or a bonded configuration. In a bonded
configuration, for example in XAUI mode, four channels are bonded together.
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
‘Transmitter Only’
channel (2)
2–10.
2–3.
2–4.
2–5.
2–6.
2–7.
2–8.
2–9.
shows the transceiver reset sequences for Cyclone IV GX devices.
Receiver CDR
in automatic
Bonded
lock mode
(3)
‘Receiver and
Transmitter’
channel
initialization reset
Transceiver
sequences
Receiver CDR
except PCI Express (PCIe)
lock mode
in manual
functional modes
(4)
All supported
‘Transmitter Only’
channel (2)
Non-Bonded
Receiver CDR
in automatic
lock mode
(5)
‘Receiver Only’
channel
Receiver CDR
Cyclone IV Device Handbook, Volume 2
in manual
lock mode
Normal Operation
Compliance and
PCI Express
(6)
Initialization/
Phases (1)
(PIPE)
Receiver CDR
in automatic
lock mode
(7)
‘Receiver and
Transmitter’
channel
Receiver CDR
lock mode
in manual
(8)
2–5