EP4CGX150CF23I7N Altera, EP4CGX150CF23I7N Datasheet - Page 255

• Manufacturer Part Number: EP4CGX150CF23I7N
• Description: IC CYCLONE IV FPGA 150K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV GXr

Specifications of EP4CGX150CF23I7N

• Number Of Logic Elements/cells: 149760
• Number Of Labs/clbs: 9360
• Total Ram Bits: 6480000
• Number Of I /o: 270
• Voltage - Supply: 1.16 V ~ 1.24 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 484-FBGA
• Family Name: Cyclone IV
• Number Of Logic Blocks/elements: 149760
• # I/os (max): 270
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 149760
• Ram Bits: 6635520
• Operating Supply Voltage (min): 1.16V
• Operating Supply Voltage (max): 1.24V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 9: SEU Mitigation in Cyclone IV Devices
Software Support
Table 9–7. CRC Block Input and Output Ports (Part 1 of 2)
© February 2010 Altera Corporation
<crcblock_name>
.clk(<clock
source>
.shiftnld
(<shiftnld
source>)
.ldsrc (<ldsrc
source>)
Port
Example 9–1
WYSIWYG atom in a Cyclone IV device.
Example 9–1. Error Detection Block Diagram
cycloneiv_crcblock<crcblock_name>
(
.clk(<clock source>),
.shiftnld(<shiftnld source>),
.ldsrc(<ldsrc source>),
.crcerror(<crcerror out destination>),
.regout(<output destination>),
);
Table 9–7
Input/Output
Input
Input
Input
Input
lists the input and output ports that you must include in the atom.
shows an example of how to define the input and output ports of a
Unique identifier for the CRC block, and represents any identifier name that is legal
for the given description language (for example, Verilog HDL, VHDL, and AHDL).
This field is required.
This signal designates the clock input of this cell. All operations of this cell are with
respect to the rising edge of the clock. Whether it is the loading of the data into the
cell or data out of the cell, it always occurs on the rising edge. This port is
required.
This signal is an input into the error detection block. If shiftnld=1, the data is
shifted from the internal shift register to the regout at each rising edge of clk.
If shiftnld=0, the shift register parallel loads either the pre-calculated CRC
value or the update register contents, depending on the ldsrc port input. To do
this, the shiftnld must be driven low for at least two clock cycles. This port is
required.
This signal is an input into the error detection block. If ldsrc=0, the
pre-computed CRC register is selected for loading into the 32-bit shift register at
the rising edge of clk when shiftnld=0. If ldsrc=1, the signature register
(result of the CRC calculation) is selected for loading into the shift register at the
rising edge of clk when shiftnld=0. This port is ignored when
shiftnld=1. This port is required.
Definition
Cyclone IV Device Handbook, Volume 1
9–9