EP4CGX150CF23I7N Altera, EP4CGX150CF23I7N Datasheet - Page 73

• Manufacturer Part Number: EP4CGX150CF23I7N
• Description: IC CYCLONE IV FPGA 150K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV GXr

Specifications of EP4CGX150CF23I7N

• Number Of Logic Elements/cells: 149760
• Number Of Labs/clbs: 9360
• Total Ram Bits: 6480000
• Number Of I /o: 270
• Voltage - Supply: 1.16 V ~ 1.24 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 484-FBGA
• Family Name: Cyclone IV
• Number Of Logic Blocks/elements: 149760
• # I/os (max): 270
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 149760
• Ram Bits: 6635520
• Operating Supply Voltage (min): 1.16V
• Operating Supply Voltage (max): 1.24V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 5: Clock Networks and PLLs in Cyclone IV Devices
Clock Networks
GCLK Network Clock Source Generation
Figure 5–2. Clock Networks and Clock Control Block Locations in EP4CGX15, EP4CGX22, and EP4CGX30 Devices
(2)
Notes to
(1) The clock networks and clock control block locations apply to all EP4CGX15, EP4CGX22, and EP4CGX30 devices except EP4CGX30 device in F484
(2) PLL_1 and PLL_2 are multipurpose PLLs while PLL_3 and PLL_4 are general purpose PLLs.
(3) There are five clock control blocks on each side.
(4) PLL_4 is only available in EP4CGX22 and EP4CGX30 devices in F324 package.
(5) The EP4CGX15 device has two DPCLK pins on three sides of the device: DPCLK2 and DPCLK5 on bottom side, DPCLK7 and DPCLK8 on the
(6) Dedicated clock pins can feed into this PLL. However, these paths are not fully compensated.
© December 2010 Altera Corporation
package.
right side, DPCLK10 and DPCLK13 on the top side of device.
HSSI
Figure
5–2:
PLL_1
PLL_2
5
5
Clock
Control
Block (3)
Figure
inputs, and clock control block location for different Cyclone IV device densities.
5–2,
4
4
5
5
DPCLK[3..2] (5)
Figure
DPCLK[13..12] (5)
GCLK[19..0]
5–3, and
20
2
2
CLK[15..12]
CLK[11..8]
Clock
Control
Block (3)
Clock
Control
Block (3)
20
20
4
4
DPCLK[5..4] (5)
20
Figure 5–4 on page 5–13
DPCLK[11..10] (5)
GCLK[19..0]
2
2
4
4
5
5
Clock
Control
Block (3)
(6)
(6)
5
5
PLL_3
PLL_4
show the Cyclone IV PLLs, clock
4
4
Cyclone IV Device Handbook, Volume 1
(4)
2
2
4
DPCLK[9..8] (5)
CLK[7..4]
DPCLK[7..6] (5)
(Note
5–11
1),