EP4CGX150CF23I7N Altera, EP4CGX150CF23I7N Datasheet - Page 92

• Manufacturer Part Number: EP4CGX150CF23I7N
• Description: IC CYCLONE IV FPGA 150K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV GXr

Specifications of EP4CGX150CF23I7N

• Number Of Logic Elements/cells: 149760
• Number Of Labs/clbs: 9360
• Total Ram Bits: 6480000
• Number Of I /o: 270
• Voltage - Supply: 1.16 V ~ 1.24 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 484-FBGA
• Family Name: Cyclone IV
• Number Of Logic Blocks/elements: 149760
• # I/os (max): 270
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 149760
• Ram Bits: 6635520
• Operating Supply Voltage (min): 1.16V
• Operating Supply Voltage (max): 1.24V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

5–30
Cyclone IV Device Handbook, Volume 1
1
Manual Override
If you are using the automatic switchover, you must switch input clocks with the
manual override feature with the clkswitch input.
Figure 5–19
when controlled by clkswitch. In this case, both clock sources are functional and
inclk0 is selected as the reference clock. A low-to-high transition of the clkswitch
signal starts the switchover sequence. The clkswitch signal must be high for at least
three clock cycles (at least three of the longer clock period if inclk0 and inclk1
have different frequencies). On the falling edge of inclk0, the reference clock of the
counter, muxout, is gated off to prevent any clock glitching. On the falling edge of
inclk1, the reference clock multiplexer switches from inclk0 to inclk1 as the PLL
reference. On the falling edge of inclk1, the reference clock multiplexer switches
from inclk0 to inclk1 as the PLL reference, and the activeclock signal changes
to indicate which clock is currently feeding the PLL.
In this mode, the activeclock signal mirrors the clkswitch signal. As both blocks
are still functional during the manual switch, neither clkbad signals go high. Because
the switchover circuit is positive edge-sensitive, the falling edge of the clkswitch
signal does not cause the circuit to switch back from inclk1 to inclk0. When the
clkswitch signal goes high again, the process repeats. The clkswitch signal and
the automatic switch only works depending on the availability of the clock that is
switched to. If the clock is unavailable, the state machine waits until the clock is
available.
When CLKSWITCH = 1, it overrides the automatic switch-over function. As long as
clkswitch signal is high, further switch-over action is blocked.
Figure 5–19. Clock Switchover Using the clkswitch Control
Note to
(1) Both inclk0 and inclk1 must be running when the clkswitch signal goes high to start a manual clock
switchover event.
Figure
5–19:
shows an example of a waveform illustrating the switchover feature
activeclock
clkswitch
clkbad0
clkbad1
muxout
inclk0
inclk1
Chapter 5: Clock Networks and PLLs in Cyclone IV Devices
(1)
© December 2010 Altera Corporation
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