EP4CGX150CF23I7N Altera, EP4CGX150CF23I7N Datasheet - Page 78

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EP4CGX150CF23I7N

Manufacturer Part Number
EP4CGX150CF23I7N
Description
IC CYCLONE IV FPGA 150K 484FBGA
Manufacturer
Altera
Series
CYCLONE® IV GXr

Specifications of EP4CGX150CF23I7N

Number Of Logic Elements/cells
149760
Number Of Labs/clbs
9360
Total Ram Bits
6480000
Number Of I /o
270
Voltage - Supply
1.16 V ~ 1.24 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
484-FBGA
Family Name
Cyclone IV
Number Of Logic Blocks/elements
149760
# I/os (max)
270
Operating Supply Voltage (typ)
1.2V
Logic Cells
149760
Ram Bits
6635520
Operating Supply Voltage (min)
1.16V
Operating Supply Voltage (max)
1.24V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
484
Package Type
FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant

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0
5–16
Figure 5–8. clkena Implementation: Output Enable
PLLs in Cyclone IV Devices
Cyclone IV Device Handbook, Volume 1
clkin
clkena
clk_out
f
1
1
The clkena circuitry controlling the output C0 of the PLL to an output pin is
implemented with two registers instead of a single register, as shown in
Figure 5–8
signal is sampled on the falling edge of the clock (clkin).
This feature is useful for applications that require low power or sleep mode.
The clkena signal can also disable clock outputs if the system is not tolerant to
frequency overshoot during PLL resynchronization.
Altera recommends using the clkena signals when switching the clock source to the
PLLs or the GCLK. The recommended sequence is:
1. Disable the primary output clock by de-asserting the clkena signal.
2. Switch to the secondary clock using the dynamic select signals of the clock control
3. Allow some clock cycles of the secondary clock to pass before reasserting the
Cyclone IV GX devices offer two variations of PLLs: general purpose PLLs and
multipurpose PLLs. Cyclone IV E devices only have the general purpose PLLs.
The general purpose PLLs are used for general-purpose applications in the FPGA
fabric and periphery such as external memory interfaces. The multipurpose PLLs are
used for clocking the transceiver blocks. When the multipurpose PLLs are not used
for transceiver clocking, they can be used for general-purpose clocking.
For more details about the multipurpose PLLs used for transceiver clocking, refer to
the
block.
clkena signal. The exact number of clock cycles you must wait before enabling
the secondary clock is design-dependent. You can build custom logic to ensure
glitch-free transition when switching between different clock sources.
Cyclone IV Transceivers
shows the waveform example for a clock output enable. The clkena
chapter.
Chapter 5: Clock Networks and PLLs in Cyclone IV Devices
© December 2010 Altera Corporation
PLLs in Cyclone IV Devices
Figure
5–7.

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