EP4CGX150CF23I7N Altera, EP4CGX150CF23I7N Datasheet - Page 42

• Manufacturer Part Number: EP4CGX150CF23I7N
• Description: IC CYCLONE IV FPGA 150K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV GXr

Specifications of EP4CGX150CF23I7N

• Number Of Logic Elements/cells: 149760
• Number Of Labs/clbs: 9360
• Total Ram Bits: 6480000
• Number Of I /o: 270
• Voltage - Supply: 1.16 V ~ 1.24 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 484-FBGA
• Family Name: Cyclone IV
• Number Of Logic Blocks/elements: 149760
• # I/os (max): 270
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 149760
• Ram Bits: 6635520
• Operating Supply Voltage (min): 1.16V
• Operating Supply Voltage (max): 1.24V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

3–6
Mixed-Width Support
Asynchronous Clear
Cyclone IV Device Handbook, Volume 1
1
Figure 3–4. Cyclone IV Devices Address Clock Enable During Write Cycle Waveform
M9K memory blocks support mixed data widths. When using simple dual-port, true
dual-port, or FIFO modes, mixed width support allows you to read and write
different data widths to an M9K memory block. For more information about the
different widths supported per memory mode, refer to
page
Cyclone IV devices support asynchronous clears for read address registers, output
registers, and output latches only. Input registers other than read address registers are
not supported. When applied to output registers, the asynchronous clear signal clears
the output registers and the effects are immediately seen. If your RAM does not use
output registers, you can still clear the RAM outputs using the output latch
asynchronous clear feature.
Asserting asynchronous clear to the read address register during a read operation
may corrupt the memory content.
Figure 3–5
Figure 3–5. Output Latch Asynchronous Clear Waveform
aclr at latch
latched address
(inside memory)
3–7.
contents at a0
contents at a1
contents at a2
contents at a3
contents at a4
contents at a5
addressstall
wraddress
aclr
clk
shows the functional waveform for the asynchronous clear feature.
q
inclock
wren
data
an
XX
a0
00
a1
XX
a0
01
a1
a2
XX
01
02
a2
XX
XX
XX
a1
02
Chapter 3: Memory Blocks in Cyclone IV Devices
a3
03
00
“Memory Modes” on
© November 2009 Altera Corporation
04
a4
a0
a4
03
a5
05
a1
04
a5
05
a6
06
Overview