EP4CGX150CF23I7N Altera, EP4CGX150CF23I7N Datasheet - Page 357

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EP4CGX150CF23I7N

Manufacturer Part Number
EP4CGX150CF23I7N
Description
IC CYCLONE IV FPGA 150K 484FBGA
Manufacturer
Altera
Series
CYCLONE® IV GXr

Specifications of EP4CGX150CF23I7N

Number Of Logic Elements/cells
149760
Number Of Labs/clbs
9360
Total Ram Bits
6480000
Number Of I /o
270
Voltage - Supply
1.16 V ~ 1.24 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
484-FBGA
Family Name
Cyclone IV
Number Of Logic Blocks/elements
149760
# I/os (max)
270
Operating Supply Voltage (typ)
1.2V
Logic Cells
149760
Ram Bits
6635520
Operating Supply Voltage (min)
1.16V
Operating Supply Voltage (max)
1.24V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
484
Package Type
FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant

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Chapter 1: Cyclone IV Transceivers Architecture
Self Test Modes
PRBS
Figure 1–74. PRBS Pattern Test Mode Datapath
Note to
(1) Serial loopback path is optional and can be enabled for the PRBS verifier to check the PRBS pattern
© December 2010 Altera Corporation
Fabric
FPGA
Figure
1–74:
Transmitter Channel PCS
Receiver Channel PCS
Transceiver
Compensation
Tx Phase
Compensation
The incremental pattern generator and verifier are 16-bits wide. The generated pattern
increments from 00 to FF and passes through the TX PCS blocks, parallel looped back
to RX PCS blocks, and checked by the verifier. The pattern is also available as serial
data at the tx_dataout port. The differential output voltage of the transmitted serial
data on the tx_dataout port is based on the selected V
data pattern is not available to the FPGA logic at the receiver for verification.
The following are the transceiver channel configuration settings in this mode:
The rx_bisterr and rx_bistdone signals indicate the status of the verifier. The
rx_bisterr signal is asserted and stays high when detecting an error in the data.
The rx_bistdone signal is asserted and stays high when the verifier either receives a
full cycle of incremental pattern or it detects an error in the receiver data. You can
reset the incremental pattern generator and verifier by asserting the
tx_digitalreset and rx_digitalreset ports, respectively.
Figure 1–74
modes. The pattern generator is located in TX PCS before the serializer, and PRBS
pattern verifier located in RX PCS after the word aligner.
FIFO
FIFO
Rx
PCS-FPGA fabric channel width: 16-bit
8B/10B blocks: Enabled
Byte serializer/deserializer: Enabled
Word aligner: Automatic synchronization state machine mode
Byte ordering: Enabled
Serializer
shows the datapath for the PRBS, high and low frequency pattern test
Ordering
Byte
Byte
Deserializer
Byte
PRBS, High Freq,
Low Freq Pattern
Encoder
8B/10B
Generator
Decoder
8B/10B
Match
FIFO
Rate
Verifier
PRBS
Aligner
Word
OD
Cyclone IV Device Handbook, Volume 2
settings. The incremental
serializer
Transmitter Channel PMA
Serializer
Receiver Channel
PMA
De-
Receiver
CDR
(1)
1–77

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