EP4CGX150CF23I7N Altera, EP4CGX150CF23I7N Datasheet - Page 380

• Manufacturer Part Number: EP4CGX150CF23I7N
• Description: IC CYCLONE IV FPGA 150K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV GXr

Specifications of EP4CGX150CF23I7N

• Number Of Logic Elements/cells: 149760
• Number Of Labs/clbs: 9360
• Total Ram Bits: 6480000
• Number Of I /o: 270
• Voltage - Supply: 1.16 V ~ 1.24 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 484-FBGA
• Family Name: Cyclone IV
• Number Of Logic Blocks/elements: 149760
• # I/os (max): 270
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 149760
• Ram Bits: 6635520
• Operating Supply Voltage (min): 1.16V
• Operating Supply Voltage (max): 1.24V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

2–14
Figure 2–9. Sample Reset Sequence of Receiver and Transmitter Channel—Receiver CDR in Manual Lock Mode
Notes to
(1) For t
(2) For t
(3) The busy signal is asserted and deasserted only during initial power up when offset cancellation occurs. In subsequent reset sequences, the
Cyclone IV Device Handbook, Volume 2
Output Status Signals
CDR Control Signals
busy signal is asserted and deasserted only if there is a read or write operation to the ALTGX_RECONFIG megafunction.
LTR_LTD_Manual
LTD_Manual
Figure
rx_analogreset
Reset Signals
rx_locktorefclk
rx_digitalreset
tx_digitalreset
rx_locktodata
pll_areset
pll_locked
busy (3)
2–9:
duration, refer to the
duration, refer to the
1
5. After the rx_freqlocked signal goes high, wait for at least t
Receiver and Transmitter Channel—Receiver CDR in Manual Lock Mode
This configuration contains both a transmitter and receiver channel. If you create a
Receiver and Transmitter instance in the ALTGX MegaWizard Plug-In Manager with
the receiver CDR in manual lock mode, use the reset sequence shown in
the rx_digitalreset signal (marker 8). At this point, the transmitter and
receiver are ready for data traffic.
1 µs
Cyclone IV Device Datasheet
Cyclone IV Device Datasheet
2
Two parallel clock cycles
3
4
5
chapter.
6
chapter.
t
LTR_LTD_Manual
(1)
Chapter 2: Cyclone IV Reset Control and Power Down
7
t
LTD_Manual
7
8
(2)
© December 2010 Altera Corporation
Transceiver Reset Sequences
LTD_Auto
, then deassert
Figure
2–9.