EP4CGX150CF23I7N Altera, EP4CGX150CF23I7N Datasheet - Page 385

• Manufacturer Part Number: EP4CGX150CF23I7N
• Description: IC CYCLONE IV FPGA 150K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV GXr

Specifications of EP4CGX150CF23I7N

• Number Of Logic Elements/cells: 149760
• Number Of Labs/clbs: 9360
• Total Ram Bits: 6480000
• Number Of I /o: 270
• Voltage - Supply: 1.16 V ~ 1.24 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 484-FBGA
• Family Name: Cyclone IV
• Number Of Logic Blocks/elements: 149760
• # I/os (max): 270
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 149760
• Ram Bits: 6635520
• Operating Supply Voltage (min): 1.16V
• Operating Supply Voltage (max): 1.24V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 2: Cyclone IV Reset Control and Power Down
Dynamic Reconfiguration Reset Sequences
Reset Sequence in Channel Reconfiguration Mode
© December 2010 Altera Corporation
2. After the PLL is reset, wait for the pll_locked signal to go high (marker 4)
3. Wait at least five parallel clock cycles after the pll_locked signal is asserted to
4. When the rx_freqlocked signal goes high (marker 7), from that point onwards,
Use the example reset sequence shown in
dynamic reconfiguration controller to change the PCS settings of the transceiver
channel. In this example, the dynamic reconfiguration is used to dynamically
reconfigure the transceiver channel configured in Basic ×1 mode with receiver CDR in
automatic lock mode.
Figure 2–12. Reset Sequence When Using the Dynamic Reconfiguration Controller to Change the
PCS Settings of the Transceiver Channel
Notes to
(1) For t
(2) The busy signal is asserted and deasserted only during initial power up when offset cancellation occurs. In
indicating that the PLL is locked to the input reference clock. After the assertion of
the pll_locked signal, deassert the tx_digitalreset signal (marker 5).
deassert the rx_analogreset signal (marker 6).
wait for at least t
(marker 8). At this point, the receiver is ready for data traffic.
subsequent reset sequences, the busy signal is asserted and deasserted only if there is a read or write operation to
the ALTGX_RECONFIG megafunction.
Reset and Control Signals
LTD_Auto
reconfig_mode_sel[2..0]
Figure
Output Status Signals
channel_reconfig_done
rx_analogreset
duration, refer to the
tx_digitalreset
rx_digitalreset
2–12:
rx_freqlocked
write_all
busy (2)
LTD_Auto
New value
time, then deassert the rx_digitalreset signal
Cyclone IV Device Datasheet
1
1
1
1
2
3
Figure 2–12
Five parallel clock cycles
4
chapter.
5
6
when you are using the
7
t
LTD_Auto
Cyclone IV Device Handbook, Volume 2
(1)
8
2–19