EP4CGX150CF23I7N Altera, EP4CGX150CF23I7N Datasheet - Page 162

• Manufacturer Part Number: EP4CGX150CF23I7N
• Description: IC CYCLONE IV FPGA 150K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV GXr

Specifications of EP4CGX150CF23I7N

• Number Of Logic Elements/cells: 149760
• Number Of Labs/clbs: 9360
• Total Ram Bits: 6480000
• Number Of I /o: 270
• Voltage - Supply: 1.16 V ~ 1.24 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 484-FBGA
• Family Name: Cyclone IV
• Number Of Logic Blocks/elements: 149760
• # I/os (max): 270
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 149760
• Ram Bits: 6635520
• Operating Supply Voltage (min): 1.16V
• Operating Supply Voltage (max): 1.24V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

7–14
Figure 7–9. Extending the OE Disable by Half a Clock Cycle for a Write Transaction
Note to
(1) The waveform reflects the software simulation result. The OE signal is an active low on the device. However, the Quartus II software implements
OCT with Calibration
PLL
Cyclone IV Device Handbook, Volume 1
the signal as an active high and automatically adds an inverter before the A
Figure
7–9:
f
f
f
1
Figure 7–9
high-impedance state by half a clock cycle during a write operation.
Cyclone IV devices support calibrated on-chip series termination (R
vertical and horizontal I/O banks. To use the calibrated OCT, you must use the RUP
and RDN pins for each R
OCT calibration block to calibrate one type of termination with the same V
given side.
For more information about the Cyclone IV devices OCT calibration block, refer to the
Cyclone IV Device I/O Features
When interfacing with external memory, the PLL is used to generate the memory
system clock, the write clock, the capture clock and the logic-core clock. The system
clock generates the DQS write signals, commands, and addresses. The write-clock is
shifted by -90° from the system clock and generates the DQ signals during writes. You
can use the PLL reconfiguration feature to calibrate the read-capture phase shift to
balance the setup and hold margins.
The PLL is instantiated in the ALTMEMPHY megafunction. All outputs of the PLL are
used when the ALTMEMPHY megafunction is instantiated to interface with external
memories. PLL reconfiguration is used in the ALTMEMPHY megafunction to
calibrate and track the read-capture phase to maintain the optimum margin.
For more information about usage of PLL outputs by the ALTMEMPHY
megafunction, refer to the
For more information about Cyclone IV PLL, refer to the
Cyclone IV Devices
from System Clock)
(outclock for DQS)
-90 phase shifted
(from logic array)
(outclock for DQ,
(from logic array)
(from logic array)
(from logic array)
o
System clock
OE for DQS
Write Clock
OE for DQ
datain_h
datain_I
DQS
DQ
illustrates how the second output enable register extends the DQS
90
chapter.
o
S
OCT control block (one for each side). You can use each
External Memory Interface
a Clock
by Half
Delay
Cycle
chapter.
Preamble
OE
D1
register D input.
D0
D0
Chapter 7: External Memory Interfaces in Cyclone IV Devices
D1
D3
D2
D2
Cyclone IV Devices Memory Interfaces Features
Handbook.
(Note 1)
D3
Postamble
Clock Networks and PLLs in
© December 2010 Altera Corporation
S
OCT) in both
CCIO
for that