EP4CGX150CF23I7N Altera, EP4CGX150CF23I7N Datasheet - Page 377
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EP4CGX150CF23I7N
Manufacturer Part Number
EP4CGX150CF23I7N
Description
IC CYCLONE IV FPGA 150K 484FBGA
Manufacturer
Altera
Series
CYCLONE® IV GXr
Datasheets
1.EP4CGX15BN11C8N.pdf
(44 pages)
2.EP4CGX15BN11C8N.pdf
(14 pages)
3.EP4CGX15BN11C8N.pdf
(478 pages)
4.EP4CGX15BN11C8N.pdf
(10 pages)
Specifications of EP4CGX150CF23I7N
Number Of Logic Elements/cells
149760
Number Of Labs/clbs
9360
Total Ram Bits
6480000
Number Of I /o
270
Voltage - Supply
1.16 V ~ 1.24 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
484-FBGA
Family Name
Cyclone IV
Number Of Logic Blocks/elements
149760
# I/os (max)
270
Operating Supply Voltage (typ)
1.2V
Logic Cells
149760
Ram Bits
6635520
Operating Supply Voltage (min)
1.16V
Operating Supply Voltage (max)
1.24V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
484
Package Type
FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP4CGX150CF23I7N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
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Chapter 2: Cyclone IV Reset Control and Power Down
Transceiver Reset Sequences
Figure 2–6. Sample Reset Sequence of Receiver Only Channel—Receiver CDR in Automatic Lock Mode
Notes to
(1) For t
(2) The busy signal is asserted and deasserted only during initial power up when offset cancellation occurs. In subsequent reset sequences, the
© December 2010 Altera Corporation
Output Status Signals
busy signal is asserted and deasserted only if there is a read or write operation to the ALTGX_RECONFIG megafunction.
LTD_Auto
Figure
Reset Signals
rx_analogreset
rx_digitalreset
rx_freqlocked
busy (2)
duration, refer to the
2–6:
As shown in
CDR automatic lock mode:
1. After power up, wait for the busy signal to be deasserted.
2. Keep the rx_digitalreset and rx_analogreset signals asserted during this
3. After the busy signal is deasserted, wait for another two parallel clock cycles, then
4. Wait for the rx_freqlocked signal to go high.
5. When rx_freqlocked goes high (marker 3), from that point onwards, wait for
time period.
deassert the rx_analogreset signal.
at least t
point, the receiver is ready to receive data.
Cyclone IV Device Datasheet
Two parallel clock cycles
1
LTD_Auto
Figure
, then de-assert the rx_digitalreset signal (marker 4). At this
2–6, perform the following reset procedure for the receiver in
2
chapter.
3
t
LTD_Auto
(1)
4
Cyclone IV Device Handbook, Volume 2
2–11
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