EP4CGX150CF23I7N Altera, EP4CGX150CF23I7N Datasheet - Page 355

• Manufacturer Part Number: EP4CGX150CF23I7N
• Description: IC CYCLONE IV FPGA 150K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV GXr

Specifications of EP4CGX150CF23I7N

• Number Of Logic Elements/cells: 149760
• Number Of Labs/clbs: 9360
• Total Ram Bits: 6480000
• Number Of I /o: 270
• Voltage - Supply: 1.16 V ~ 1.24 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 484-FBGA
• Family Name: Cyclone IV
• Number Of Logic Blocks/elements: 149760
• # I/os (max): 270
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 149760
• Ram Bits: 6635520
• Operating Supply Voltage (min): 1.16V
• Operating Supply Voltage (max): 1.24V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 1: Cyclone IV Transceivers Architecture
Loopback
Reverse Serial Loopback
Figure 1–72. Reverse Serial Loopback
Notes to
(1) Grayed-Out Blocks are Not Active in this mode.
(2) Post-CDR reverse serial loopback path.
(3) Pre-CDR reverse serial loopback path.
© December 2010 Altera Corporation
Figure
1–72:
1
1
Fabric
FPGA
The reverse serial loopback mode is available for all functional modes except for
XAUI mode. The two reverse serial loopback options from the receiver to the
transmitter are:
■
■
The received data is also available to the FPGA logic. In the transmitter channel, only
the transmitter buffer is active.
The transmitter pre-emphasis feature is not available in reverse serial loopback (pre-
CDR) mode.
Reverse serial loopback modes can only be dynamically enabled or disabled during
user mode by performing a dynamic channel reconfiguration.
Figure 1–72
Pre-CDR mode where data received through the RX input buffer is looped back to
the TX output buffer using the Reverse serial loopback (pre-CDR) option
Post-CDR mode where retimed data through the receiver CDR from the RX input
buffer is looped back to the TX output buffer using the Reverse serial loopback
option
To FPGA fabric
for verification
shows the two paths in reverse serial loopback mode.
(Note 1)
Transceiver
Tx PCS
Rx PCS
Tx PMA
Rx PMA
Deserializer
Serializer
(2)
Tx PMA
CDR
(3)
Cyclone IV Device Handbook, Volume 2
1–75