EP4CGX150CF23I7N Altera, EP4CGX150CF23I7N Datasheet - Page 373

• Manufacturer Part Number: EP4CGX150CF23I7N
• Description: IC CYCLONE IV FPGA 150K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV GXr

Specifications of EP4CGX150CF23I7N

• Number Of Logic Elements/cells: 149760
• Number Of Labs/clbs: 9360
• Total Ram Bits: 6480000
• Number Of I /o: 270
• Voltage - Supply: 1.16 V ~ 1.24 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 484-FBGA
• Family Name: Cyclone IV
• Number Of Logic Blocks/elements: 149760
• # I/os (max): 270
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 149760
• Ram Bits: 6635520
• Operating Supply Voltage (min): 1.16V
• Operating Supply Voltage (max): 1.24V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 2: Cyclone IV Reset Control and Power Down
Transceiver Reset Sequences
Figure 2–4. Sample Reset Sequence for Bonded Configuration Receiver and Transmitter Channels—Receiver CDR in
Automatic Lock Mode
Notes to
(1) The number of rx_freqlocked[n] signals depend on the number of channels configured. n=number of channels.
(2) For t
(3) The busy signal is asserted and deasserted only during initial power up when offset cancellation occurs. In subsequent reset sequences, the
© December 2010 Altera Corporation
Output Status Signals
busy signal is asserted and deasserted only if there is a read or write operation to the ALTGX_RECONFIG megafunction.
rx_freqlocked[n] (1)
LTD_Auto
Figure
rx_freqlocked[0]
Reset Signals
rx_analogreset
rx_digitalreset
tx_digitalreset
pll_locked
pll_areset
busy (3)
duration, refer to the
2–4:
1
As shown in
Only channel configuration:
1. After power up, assert pll_areset for a minimum period of 1 s (the time
2. Keep the tx_digitalreset signal asserted during this time period. After you
3. When the multipurpose PLL locks, as indicated by the pll_locked signal going
Receiver and Transmitter Channel—Receiver CDR in Automatic Lock Mode
This configuration contains both a transmitter and receiver channel. When the
receiver CDR is in automatic lock mode, use the reset sequence shown in
between markers 1 and 2).
de-assert the pll_areset signal, the multipurpose PLL starts locking to the
transmitter input reference clock.
high (marker 3), de-assert the tx_digitalreset signal (marker 4). At this point,
the transmitter is ready for transmitting data.
1 µs
Cyclone IV Device Datasheet
Figure
2
3
2–3, perform the following reset procedure for the Transmitter
4
Two parallel clock cycles
5
chapter.
6
7
7
t LTD_Auto
(2)
8
Cyclone IV Device Handbook, Volume 2
Figure
2–4.
2–7