EP4CGX150CF23I7N Altera, EP4CGX150CF23I7N Datasheet - Page 161

• Manufacturer Part Number: EP4CGX150CF23I7N
• Description: IC CYCLONE IV FPGA 150K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV GXr

Specifications of EP4CGX150CF23I7N

• Number Of Logic Elements/cells: 149760
• Number Of Labs/clbs: 9360
• Total Ram Bits: 6480000
• Number Of I /o: 270
• Voltage - Supply: 1.16 V ~ 1.24 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 484-FBGA
• Family Name: Cyclone IV
• Number Of Logic Blocks/elements: 149760
• # I/os (max): 270
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 149760
• Ram Bits: 6635520
• Operating Supply Voltage (min): 1.16V
• Operating Supply Voltage (max): 1.24V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 7: External Memory Interfaces in Cyclone IV Devices
Cyclone IV Devices Memory Interfaces Features
DDR Output Registers
Figure 7–8. Cyclone IV Dedicated Write DDIO
© December 2010 Altera Corporation
f
-90° Shifted Clock
A dedicated write DDIO block is implemented in the DDR output and output enable
paths.
Figure 7–8
the I/O element (IOE) registers.
The two DDR output registers are located in the I/O element (IOE) block. Two serial
data streams routed through datain_l and datain_h, are fed into two registers,
output register Ao and output register Bo, respectively, on the same clock
edge. The output from output register Ao is captured on the falling edge of the
clock, while the output from output register Bo is captured on the rising edge of
the clock. The registered outputs are multiplexed by the common clock to drive the
DDR output pin at twice the data rate.
The DDR output enable path has a similar structure to the DDR output path in the
IOE block. The second output enable register provides the write preamble for the DQS
strobe in DDR external memory interfaces. This active-low output enable register
extends the high-impedance state of the pin by half a clock cycle to provide the
external memory’s DQS write preamble time specification.
For more information about Cyclone IV IOE registers, refer to the
I/O Features
Output Enable
datain_h
datain_l
shows how a Cyclone IV dedicated write DDIO block is implemented in
chapter.
Output Register A
Output Register B
Output Enable
Register A
Output Enable
Register B
Register
Register
Register
Register
IOE
IOE
IOE
IOE
DDR Output Enable Registers
DDR Output Registers
OE
OE
O
O
data0
data1
data1
data0
®
Cyclone IV Device Handbook, Volume 1
DQ or DQS
Cyclone IV Device
7–13