EP4CGX150CF23I7N Altera, EP4CGX150CF23I7N Datasheet - Page 314

• Manufacturer Part Number: EP4CGX150CF23I7N
• Description: IC CYCLONE IV FPGA 150K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV GXr

Specifications of EP4CGX150CF23I7N

• Number Of Logic Elements/cells: 149760
• Number Of Labs/clbs: 9360
• Total Ram Bits: 6480000
• Number Of I /o: 270
• Voltage - Supply: 1.16 V ~ 1.24 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 484-FBGA
• Family Name: Cyclone IV
• Number Of Logic Blocks/elements: 149760
• # I/os (max): 270
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 149760
• Ram Bits: 6635520
• Operating Supply Voltage (min): 1.16V
• Operating Supply Voltage (max): 1.24V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

1–34
Cyclone IV Device Handbook, Volume 2
1
When implementing ×2 bonded channel configuration in a transceiver block,
remaining channels 2 and 3 are available to implement other non-bonded channel
configuration.
Figure 1–36
low-speed clock distributions for transceivers in F324 and smaller packages, and in
F484 and larger packages in bonded (×2 and ×4) channel configuration.
Figure 1–36. Clock Distribution in Bonded (×2 and ×4) Channel Configuration for Transceivers in
F324 and Smaller Packages.
Notes to
(1) Transceiver channels 2 and 3 are not available for devices in F169 and smaller packages.
(2) High-speed clock.
(3) Low-speed clock.
(4) Bonded common low-speed clock path.
Figure 1–36
Transceiver
GXBL0
Block
and
2 Bonded Channel Configuration
:
Ch3
Ch2
Ch1
Ch0
Figure 1–37
(1)
(1)
MPLL_2
MPLL_1
TX PMA
TX PMA
TX PMA
TX PMA
(4)
show the independent high-speed clock and bonded
(3)
(2)
Transceiver
GXBL0
Block
Chapter 1: Cyclone IV Transceivers Architecture
4 Bonded Channel Configuration
Ch3
Ch2
Ch1
Ch0
(1)
(1)
MPLL_2
MPLL_1
TX PMA
TX PMA
TX PMA
TX PMA
© December 2010 Altera Corporation
Transceiver Clocking Architecture
(4)
(2)
(3)