EP4CGX150CF23I7N Altera, EP4CGX150CF23I7N Datasheet - Page 322

• Manufacturer Part Number: EP4CGX150CF23I7N
• Description: IC CYCLONE IV FPGA 150K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV GXr

Specifications of EP4CGX150CF23I7N

• Number Of Logic Elements/cells: 149760
• Number Of Labs/clbs: 9360
• Total Ram Bits: 6480000
• Number Of I /o: 270
• Voltage - Supply: 1.16 V ~ 1.24 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 484-FBGA
• Family Name: Cyclone IV
• Number Of Logic Blocks/elements: 149760
• # I/os (max): 270
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 149760
• Ram Bits: 6635520
• Operating Supply Voltage (min): 1.16V
• Operating Supply Voltage (max): 1.24V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

1–42
PCI-Express Hard IP Block
Cyclone IV Device Handbook, Volume 2
f
Figure 1–42
PHY MAC, Data Link Layer, and Transaction Layer for PCIe interfaces. The PIPE
interface is used as the interface between the transceiver and the hard IP block.
Figure 1–42. PCI Express Hard IP High-Level Block Diagram
The hard IP block supports 1, 2, or 4 initial lane configurations with a maximum
payload of 256 bytes at Gen1 frequency. The application interface is 64 bits with a data
width of 16 bits per channel running at up to 125 MHz. As a hard macro and a verified
block, it uses very few FPGA resources, while significantly reducing design risk and
the time required to achieve timing closure. It is compliant with the PCI Express Base
Specification 1.1. You do not have to pay a licensing fee to use this module.
Configuring the hard IP block requires using the PCI Express Compiler.
For more information about the hard IP block, refer to the
Guide.
Figure 1–43
hard IP block.
Figure 1–43. PCIe with Hard IP Block Lane Placement Requirements
Note to
(1) Applicable for PCIe ×1, ×2, and ×4 implementations with hard IP blocks only.
Figure 1–43
shows the block diagram of the PCIe hard IP block implementing the
shows the lane placement requirements when implementing PCIe with
:
Buffer
Retry
PCIe Lane 3
PCIe Lane 2
PCIe Lane 1
PCIe Lane 0
Channel
Virtual
Buffer
RX
Clock & Reset Selection
PCIe Protocol Stack
PCIe Hard IP
Block GXBL0
Transceiver
Channel 3
Channel 2
Channel 1
Channel 0
Chapter 1: Cyclone IV Transceivers Architecture
hard IP
PCIe
© December 2010 Altera Corporation
Interface
PCI Express Compiler User
TL
(Note 1)
Reconfig
Mnmt IF
Adapter
Local
(LMI)
PCIe
PCI-Express Hard IP Block