EP4CGX150CF23I7N Altera, EP4CGX150CF23I7N Datasheet - Page 160

• Manufacturer Part Number: EP4CGX150CF23I7N
• Description: IC CYCLONE IV FPGA 150K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV GXr

Specifications of EP4CGX150CF23I7N

• Number Of Logic Elements/cells: 149760
• Number Of Labs/clbs: 9360
• Total Ram Bits: 6480000
• Number Of I /o: 270
• Voltage - Supply: 1.16 V ~ 1.24 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 484-FBGA
• Family Name: Cyclone IV
• Number Of Logic Blocks/elements: 149760
• # I/os (max): 270
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 149760
• Ram Bits: 6635520
• Operating Supply Voltage (min): 1.16V
• Operating Supply Voltage (max): 1.24V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

7–12
Cyclone IV Devices Memory Interfaces Features
DDR Input Registers
Figure 7–7. Cyclone IV DDR Input Registers
Cyclone IV Device Handbook, Volume 1
dataout_h
dataout_l
This section discusses Cyclone IV memory interfaces, including DDR input registers,
DDR output registers, OCT, and phase-lock loops (PLLs).
The DDR input registers are implemented with three internal logic element (LE)
registers for every DQ pin. These LE registers are located in the logic array block
(LAB) adjacent to the DDR input pin.
Figure 7–7
These DDR input registers are implemented in the core of devices. The DDR data is
first fed to two registers, input register A
■
■
■
The data from the DDR input register is fed to two registers, sync_reg_h and
sync_reg_l, then the data is typically transferred to a FIFO block to synchronize the
two data streams to the rising edge of the system clock. Because the read-capture
clock is generated by the PLL, the read-data strobe signal (DQS or CQ) is not used
during read operation in Cyclone IV devices; hence, postamble is not a concern in this
case.
Input register A
Input register B
Register C
illustrates Cyclone IV DDR input registers.
I
aligns the data before it is synchronized with the system clock
I
I
captures the DDR data present during the falling edge of the clock
captures the DDR data present during the rising edge of the clock
Register C
Register
DDR Input Registers in Cyclone IV Device
LE
I
Input Register A
Input Register B
neg_reg_out
Register
Register
Chapter 7: External Memory Interfaces in Cyclone IV Devices
LE
LE
I
and input register B
I
I
Cyclone IV Devices Memory Interfaces Features
Capture Clock
© December 2010 Altera Corporation
I
.
PLL
DQ