EP4CGX150CF23I7N Altera, EP4CGX150CF23I7N Datasheet - Page 209

• Manufacturer Part Number: EP4CGX150CF23I7N
• Description: IC CYCLONE IV FPGA 150K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV GXr

Specifications of EP4CGX150CF23I7N

• Number Of Logic Elements/cells: 149760
• Number Of Labs/clbs: 9360
• Total Ram Bits: 6480000
• Number Of I /o: 270
• Voltage - Supply: 1.16 V ~ 1.24 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 484-FBGA
• Family Name: Cyclone IV
• Number Of Logic Blocks/elements: 149760
• # I/os (max): 270
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 149760
• Ram Bits: 6635520
• Operating Supply Voltage (min): 1.16V
• Operating Supply Voltage (max): 1.24V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 8: Configuration and Remote System Upgrades in Cyclone IV Devices
Configuration
Table 8–11. FPP Timing Parameters for Cyclone IV Devices (Part 1 of 2)
© December 2010 Altera Corporation
t
t
t
t
t
t
CF2CD
CF2ST0
CFG
STATUS
CF2ST1
CF2CK
Symbol
nCONFIG low to
CONF_DONE low
nCONFIG low to
nSTATUS low
nCONFIG low
pulse width
nSTATUS low
pulse width
nCONFIG high to
nSTATUS high
nCONFIG high to
first rising edge on
DCLK
Parameter
FPP Configuration Timing
Figure 8–22
external host.
Figure 8–22. FPP Configuration Timing Waveform
Notes to
(1) The beginning of this waveform shows the device in user mode. In user mode, nCONFIG, nSTATUS, and
(2) After power up, the Cyclone IV device holds nSTATUS low during POR delay.
(3) After power up, before and during configuration, CONF_DONE is low.
(4) Do not leave DCLK floating after configuration. It must be driven high or low, whichever is more convenient.
(5) DATA[7..0] is available as a user I/O pin after configuration; the state of the pin depends on the dual-purpose pin
Table 8–11
CONF_DONE are at logic-high levels. When nCONFIG is pulled low, a reconfiguration cycle begins.
settings.
CONF_DONE (3)
Figure
nSTATUS (2)
INIT_DONE
DATA[7..0]
nCONFIG
DCLK
User I/O
lists the FPP configuration timing parameters for Cyclone IV devices.
shows the timing waveform for the FPP configuration when using an
8–22:
Cyclone IV
Tri-stated with internal pull-up resistor
t
t
CFG
CF2CD
t
CF2ST1
t
(2)
Minimum
CF2ST0
230
t
CF2CK
t
ST2CK
500
—
—
45
—
t
Byte 0
STATUS
(4)
t
Cyclone IV E
CH
t
CLK
t
DSU
t
Byte 1
CL
t
DH
Byte 2
Byte 3
(3)
(Note 1)
(Note 1)
Cyclone IV
Byte n-1
(2)
Byte n
Maximum
Cyclone IV Device Handbook, Volume 1
230
230
500
500
—
—
t
CD2UM
(4)
(5)
Cyclone IV E
(5)
User Mode
User Mode
(4)
(3)
Unit
ns
ns
ns
µs
µs
µs
8–43