EP4CGX150CF23I7N Altera, EP4CGX150CF23I7N Datasheet - Page 404

• Manufacturer Part Number: EP4CGX150CF23I7N
• Description: IC CYCLONE IV FPGA 150K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV GXr

Specifications of EP4CGX150CF23I7N

• Number Of Logic Elements/cells: 149760
• Number Of Labs/clbs: 9360
• Total Ram Bits: 6480000
• Number Of I /o: 270
• Voltage - Supply: 1.16 V ~ 1.24 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 484-FBGA
• Family Name: Cyclone IV
• Number Of Logic Blocks/elements: 149760
• # I/os (max): 270
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 149760
• Ram Bits: 6635520
• Operating Supply Voltage (min): 1.16V
• Operating Supply Voltage (max): 1.24V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

3–14
Figure 3–5. Read Transaction Waveform—Use ‘logical_channel_address port’ Option
Notes to
(1) In this waveform example, you want to read from only the transmitter portion of the channel.
(2) In this waveform example, the number of channels connected to the dynamic reconfiguration controller is four. Therefore, the
Cyclone IV Device Handbook, Volume 2
logical_channel_address port is 2 bits wide.
Figure
logical_channel_address [1:0]
3–5:
1
rx_tx_duplex_sel [1:0]
tx_vodctrl_out [2:0]
Figure 3–5
Simultaneous write and read transactions are not allowed.
Method 2: Writing the Same Control Signals to Control All the Transceiver Channels
This method does not require the logical_channel_address port. The PMA controls
of all the transceiver channels connected to the ALTGX_RECONFIG instance are
reconfigured.
The Use the same control signal for all the channels option is available on the
Analog controls tab of the ALTGX_RECONFIG MegaWizard Plug-In Manager. If you
enable this option, the width of the PMA control ports are fixed as follows:
PMA Control Ports Used in a Write Transaction
■
■
■
■
PMA Control Ports Used in a Read Transaction
■
■
■
■
tx_vodctrl is fixed to 3 bits
tx_preemp is fixed to 5 bits
rx_eqdcgain is fixed to 2 bits
rx_eqctrl is fixed to 4 bits
tx_vodctrl_out is 3 bits per channel
tx_preemp_out is 5 bits per channel
rx_eqdcgain_out is 2 bits per channel
rx_eqctrl_out is 4 bits per channel
reconfig_clk
data_valid
read
busy
shows the read transaction waveform for Method 1.
(1)
(2)
2'b00
2'b00
3'b111
2'b10
2'b01
Chapter 3: Cyclone IV Dynamic Reconfiguration
3'bXXX
© December 2010 Altera Corporation
Dynamic Reconfiguration Modes
3'b001