EP4CGX150CF23I7N Altera, EP4CGX150CF23I7N Datasheet - Page 332

• Manufacturer Part Number: EP4CGX150CF23I7N
• Description: IC CYCLONE IV FPGA 150K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV GXr

Specifications of EP4CGX150CF23I7N

• Number Of Logic Elements/cells: 149760
• Number Of Labs/clbs: 9360
• Total Ram Bits: 6480000
• Number Of I /o: 270
• Voltage - Supply: 1.16 V ~ 1.24 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 484-FBGA
• Family Name: Cyclone IV
• Number Of Logic Blocks/elements: 149760
• # I/os (max): 270
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 149760
• Ram Bits: 6635520
• Operating Supply Voltage (min): 1.16V
• Operating Supply Voltage (max): 1.24V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

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Cyclone IV Device Handbook, Volume 2
f
Lane Synchronization
In PIPE mode, the word aligner is configured in automatic synchronization state
machine mode that complies with the PCIe specification.
synchronization state machine parameters that implement the PCIe-compliant
synchronization.
Table 1–16. Synchronization State Machine Parameters
Clock Rate Compensation
In PIPE mode, the rate match FIFO compensates up to ±300 PPM (600 PPM total)
difference between the upstream transmitter and the local receiver reference clock. In
PIPE mode, the rate match FIFO operation is compliant to the version 2.0 of the PCIe
Base Specification. The PCIe protocol requires the receiver to recognize a skip (SKP)
ordered set, and inserts or deletes only one SKP symbol per SKP ordered set received
to prevent the rate match FIFO from overflowing or underflowing. The SKP ordered
set is a /K28.5/ comma (COM) symbol followed by one to five consecutive /K28.0/
SKP symbols, which are sent by transmitter during the inter-packet gap.
The rate match operation begins after the synchronization state machine in the word
aligner indicates synchronization is acquired, as indicated with logic high on
rx_syncstatus signal. Rate match FIFO insertion and deletion events are
communicated to FPGA fabric on the pipestatus[2..0] port from each channel.
Low-Latency Synchronous PCIe
In PIPE mode, the Cyclone IV GX transceiver supports a lower latency in synchronous
PCIe by reducing the latency across the rate match FIFO. In synchronous PCIe, the
system uses a common reference clocking that gives a 0 PPM difference between the
upstream transmitter's and local receiver's reference clock.
When using common reference clocking, the transceiver supports spread-spectrum
clocking. For more information about the SSC support in PCIe Express (PIPE) mode,
refer to the
Fast Recovery from P0s State
The PCIe protocol defines fast training sequences for bit and byte synchronization to
transition from L0s to L0 (PIPE P0s to P0) power states. The PHY must acquire bit and
byte synchronization when transitioning from L0s to L0 state between 16 ns to 4 µs.
Each Cyclone IV GX receiver channel has built-in fast recovery circuit that allows the
receiver to meet the requirement when enabled.
Number of valid synchronization (/K28.5/) code groups received to achieve
synchronization
Number of erroneous code groups received to lose synchronization
Number of continuous good code groups received to reduce the error count by
one
Note to
(1) The word aligner supports 10-bit pattern lengths in PIPE mode.
Table
Cyclone IV Device Data
1–16:
Parameter
Sheet.
Chapter 1: Cyclone IV Transceivers Architecture
(Note 1)
Table 1–16
© December 2010 Altera Corporation
Transceiver Functional Modes
lists the
Value
16
17
4