EP4CGX150CF23I7N Altera, EP4CGX150CF23I7N Datasheet - Page 149

• Manufacturer Part Number: EP4CGX150CF23I7N
• Description: IC CYCLONE IV FPGA 150K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV GXr

Specifications of EP4CGX150CF23I7N

• Number Of Logic Elements/cells: 149760
• Number Of Labs/clbs: 9360
• Total Ram Bits: 6480000
• Number Of I /o: 270
• Voltage - Supply: 1.16 V ~ 1.24 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 484-FBGA
• Family Name: Cyclone IV
• Number Of Logic Blocks/elements: 149760
• # I/os (max): 270
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 149760
• Ram Bits: 6635520
• Operating Supply Voltage (min): 1.16V
• Operating Supply Voltage (max): 1.24V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Figure 7–1. Cyclone IV Devices External Memory Data Path
Note to
(1) All clocks shown here are global clocks.
© December 2010 Altera Corporation
CYIV-51007-2.2
Figure
7–1:
f
PLL
1
-90° Shifted Clock
OE
This chapter describes the memory interface pin support and the external memory
interface features of Cyclone
In addition to an abundant supply of on-chip memory, Cyclone IV devices can easily
interface with a broad range of external memory devices, including DDR2 SDRAM,
DDR SDRAM, and QDR II SRAM. External memory devices are an important system
component of a wide range of image processing, storage, communications, and
general embedded applications.
Altera recommends that you construct all DDR2 or DDR SDRAM external memory
interfaces using the Altera
controller function using the Altera DDR2 or DDR SDRAM memory controllers,
third-party controllers, or a custom controller for unique application needs.
Cyclone IV devices support QDR II interfaces electrically, but Altera does not supply
controller or physical layer (PHY) megafunctions for QDR II interfaces.
This chapter includes the following sections:
■
■
For more information about supported maximum clock rate, device and pin planning,
IP implementation, and device termination, refer to the
Handbook.
Figure 7–1
in Cyclone IV devices.
Register
System Clock
IOE
Register
“Cyclone IV Devices Memory Interfaces Pin Support” on page 7–2
“Cyclone IV Devices Memory Interfaces Features” on page 7–12
IOE
GND
V CC
Capture Clock
shows the block diagram of a typical external memory interface data path
Register
Register
IOE
IOE
DQS/CQ/CQn
®
OE
ALTMEMPHY megafunction. You can implement the
®
IV devices.
7. External Memory Interfaces in
Register
(Note 1)
IOE
Register
IOE
DataA
DataB
Register
Register
IOE
IOE
DQ
Cyclone IV Devices
External Memory Interface
Cyclone IV Device Handbook, Volume 1
Register
Register
LE
LE
Register
LE