EP4CGX150CF23I7N Altera, EP4CGX150CF23I7N Datasheet - Page 458
![no-image](/images/manufacturer_photos/0/0/40/altera_sml.jpg)
EP4CGX150CF23I7N
Manufacturer Part Number
EP4CGX150CF23I7N
Description
IC CYCLONE IV FPGA 150K 484FBGA
Manufacturer
Altera
Series
CYCLONE® IV GXr
Datasheets
1.EP4CGX15BN11C8N.pdf
(44 pages)
2.EP4CGX15BN11C8N.pdf
(14 pages)
3.EP4CGX15BN11C8N.pdf
(478 pages)
4.EP4CGX15BN11C8N.pdf
(10 pages)
Specifications of EP4CGX150CF23I7N
Number Of Logic Elements/cells
149760
Number Of Labs/clbs
9360
Total Ram Bits
6480000
Number Of I /o
270
Voltage - Supply
1.16 V ~ 1.24 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
484-FBGA
Family Name
Cyclone IV
Number Of Logic Blocks/elements
149760
# I/os (max)
270
Operating Supply Voltage (typ)
1.2V
Logic Cells
149760
Ram Bits
6635520
Operating Supply Voltage (min)
1.16V
Operating Supply Voltage (max)
1.24V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
484
Package Type
FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP4CGX150CF23I7N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
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1–24
Table 1–25. PLL Specifications for Cyclone IV Devices
Cyclone IV Device Handbook, Volume 3
f
f
f
f
t
f
(3)
f
t
t
t
t
t
t
t
t
t
IN
INPFD
VCO
INDUTY
INJITTER_CCJ
OUT_EXT
OUT
OUTDUTY
LOCK
DLOCK
OUTJITTER_PERIOD_DEDCLK
OUTJITTER_CCJ_DEDCLK
OUTJITTER_PERIOD_IO
OUTJITTER_CCJ_IO
PLL_PSERR
ARESET
(3)
(4)
(to global clock)
(external clock output)
(5)
Symbol
(6)
(6)
(6)
(6)
PLL Specifications
Table 1–25
commercial junction temperature range (0°C to 85°C), the industrial junction
temperature range (–40°C to 100°C), and the automotive junction temperature range
(–40°C to 125°C). For more information about the PLL block, refer to
page
1–38.
Input clock frequency (–6, –7, –8 speed grades)
Input clock frequency (–8L speed grade)
Input clock frequency (–9L speed grade)
PFD input frequency
PLL internal VCO operating range
Input clock duty cycle
Input clock cycle-to-cycle jitter
F
F
PLL output frequency
PLL output frequency (–6 speed grade)
PLL output frequency (–7 speed grade)
PLL output frequency (–8 speed grade)
PLL output frequency (–8L speed grade)
PLL output frequency (–9L speed grade)
Duty cycle for external clock output (when set to 50%)
Time required to lock from end of device configuration
Time required to lock dynamically (after switchover,
reconfiguring any non-post-scale counters/delays or
areset is deasserted)
Dedicated clock output period jitter
F
F
Dedicated clock output cycle-to-cycle jitter
F
F
Regular I/O period jitter
F
F
Regular I/O cycle-to-cycle jitter
F
F
Accuracy of PLL phase shift
Minimum pulse width on areset signal.
REF
REF
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
100 MHz
< 100 MHz
100 MHz
< 100 MHz
100 MHz
< 100 MHz
100 MHz
< 100 MHz
100 MHz
< 100 MHz
lists the PLL specifications for Cyclone IV devices when operating in the
Parameter
(Note
1),
(2)
(Part 1 of 2)—Preliminary
Chapter 1: Cyclone IV Device Datasheet
Min
600
40
—
—
—
—
—
—
—
—
45
—
—
—
—
—
—
—
—
—
—
—
10
© December 2010 Altera Corporation
5
5
5
5
Typ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
50
—
—
—
—
—
—
—
—
—
—
—
—
Switching Characteristics
“Glossary” on
472.5
402.5
472.5
472.5
1300
±750
Max
0.15
362
265
325
450
362
265
300
300
650
650
±50
60
55
30
30
75
75
—
1
1
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Unit
mUI
mUI
mUI
mUI
ms
ms
UI
ps
ps
ps
ps
ps
ps
ns
%
%
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