EP4CGX150CF23I7N Altera, EP4CGX150CF23I7N Datasheet - Page 331

• Manufacturer Part Number: EP4CGX150CF23I7N
• Description: IC CYCLONE IV FPGA 150K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV GXr

Specifications of EP4CGX150CF23I7N

• Number Of Logic Elements/cells: 149760
• Number Of Labs/clbs: 9360
• Total Ram Bits: 6480000
• Number Of I /o: 270
• Voltage - Supply: 1.16 V ~ 1.24 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 484-FBGA
• Family Name: Cyclone IV
• Number Of Logic Blocks/elements: 149760
• # I/os (max): 270
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 149760
• Ram Bits: 6635520
• Operating Supply Voltage (min): 1.16V
• Operating Supply Voltage (max): 1.24V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 1: Cyclone IV Transceivers Architecture
Transceiver Functional Modes
© December 2010 Altera Corporation
Figure 1–50. Example of Successful Receiver Detect Operation
Figure 1–51. Example of Unsuccessful Receiver Detect Operation
Electrical Idle Control
The Cyclone IV GX transceivers support transmitter buffer in electrical idle state
using the tx_forceelecidle port. During electrical idle, the transmitter buffer
differential and common mode output voltage levels are compliant to the PCIe Base
Specification 2.0 for Gen1 signaling rate.
Figure 1–52
port and the transmitter buffer output on the tx_dataout port.
Figure 1–52. Transmitter Buffer Electrical Idle State
Notes to
(1) The protocol requires the transmitter buffer to transition to a valid electrical idle after sending an electrical idle
(2) The protocol requires transmitter buffer to stay in electrical idle for a minimum of 20 ns for Gen1 signaling rate.
Signal Detect at Receiver
In PIPE mode, signal detection is supported with the built-in signal threshold
detection circuitry. When electrical idle inference is not enabled, the
rx_signaldetect signal is inverted and available as pipeelecidle port in the
PIPE interface.
ordered set within 8 ns.
tx_forcelecidle
Figure
tx_dataout
shows the relationship between assertion of the tx_forceelecidle
1–52:
tx_detectrxloopback
tx_detectrxloopback
pipephydonestatus
pipephydonestatus
powerdown[1..0]
powerdown[1..0]
pipestatus[2..0]
pipestatus[2..0]
<8 ns (1)
3'b000
2'b10(P1)
2'b10(P1)
3'b000
>20 ns (2)
3'b011
Cyclone IV Device Handbook, Volume 2
1–51