EP4CGX150CF23I7N Altera, EP4CGX150CF23I7N Datasheet - Page 366

• Manufacturer Part Number: EP4CGX150CF23I7N
• Description: IC CYCLONE IV FPGA 150K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV GXr

Specifications of EP4CGX150CF23I7N

• Number Of Logic Elements/cells: 149760
• Number Of Labs/clbs: 9360
• Total Ram Bits: 6480000
• Number Of I /o: 270
• Voltage - Supply: 1.16 V ~ 1.24 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 484-FBGA
• Family Name: Cyclone IV
• Number Of Logic Blocks/elements: 149760
• # I/os (max): 270
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 149760
• Ram Bits: 6635520
• Operating Supply Voltage (min): 1.16V
• Operating Supply Voltage (max): 1.24V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

1–86
Document Revision History
Table 1–30. Document Revision History
Cyclone IV Device Handbook, Volume 2
December 2010
November 2010
July 2010
Date
Revision
Table 1–30
3.1
3.2
3.0
lists the revision history for this chapter.
■
■
■
■
■
Updated Introductory information.
■
■
Updated for the Quartus II software version 10.1 release.
Updated
Table
Updated
“Clock Data
Receiver PCS
“Channel
Modes”
Added
Updated
Figure
Updated information for the Quartus II software version 10.0 release.
Reset control, power down, and dynamic reconfiguration information moved to
new Cyclone IV Reset Control and Power Down and Cyclone IV Dynamic
Reconfiguration chapters.
1–26,
1–70,
Figure
sections.
Table
“8B/10B
Figure
Deskewing”,
Table
Recovery”,
Figure
1–9,
Feature”,
1–1,
1–53,
1–27,
Encoder”,
Figure
Table
1–71,
Figure
“Lane
“Input Reference
“Miscellaneous Transmitter PCS
Table
1–5,
1–10,
Figure
“Transmitter Output
1–55,
Synchronization”,
1–28, and
Table
Figure
Changes Made
1–72,
Figure
1–11,
1–19,
Figure
Table
Clocking”,
Chapter 1: Cyclone IV Transceivers Architecture
1–59,
Table
Figure
1–73, and
1–29.
“Serial
Figure
1–14,
Buffer”,
© December 2010 Altera Corporation
“PCI Express (PIPE)
1–20, and
Loopback”, and
Table
1–60,
Features”,
Figure
“Receiver Input
1–24,
Document Revision History
Figure
Figure
1–74.
Table
“Miscellaneous
1–69,
1–43.
“Self Test
Mode”,
1–25,
Buffer”,