EP4CGX150CF23I7N Altera, EP4CGX150CF23I7N Datasheet - Page 290

• Manufacturer Part Number: EP4CGX150CF23I7N
• Description: IC CYCLONE IV FPGA 150K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV GXr

Specifications of EP4CGX150CF23I7N

• Number Of Logic Elements/cells: 149760
• Number Of Labs/clbs: 9360
• Total Ram Bits: 6480000
• Number Of I /o: 270
• Voltage - Supply: 1.16 V ~ 1.24 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 484-FBGA
• Family Name: Cyclone IV
• Number Of Logic Blocks/elements: 149760
• # I/os (max): 270
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 149760
• Ram Bits: 6635520
• Operating Supply Voltage (min): 1.16V
• Operating Supply Voltage (max): 1.24V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

1–10
Receiver Channel Datapath
Receiver Input Buffer
Cyclone IV Device Handbook, Volume 2
The following sections describe the Cyclone IV GX receiver channel datapath
architecture as shown in
Table 1–2
buffer.
Table 1–2. Electrical Features Supported by the Receiver Input Buffer
The high-speed serial link can be AC- or DC-coupled, depending on the serial
protocol implementation. In an AC-coupled link, the AC-coupling capacitor blocks
the transmitter DC common mode voltage as shown in
and on-chip biasing circuitry automatically restores the common mode voltage. The
biasing circuitry is also enabled by enabling OCT. If you disable the OCT, then you
must externally terminate and bias the receiver. AC-coupled links are required for
PCIe, GbE, Serial RapidIO, SDI, XAUI, SATA, V-by-One and Display Port protocols.
1.4-V PCML
1.5-V PCML
2.5-V PCML
LVPECL
LVDS
Note to
(1) DC coupling is supported for LVDS with lower on-chip common mode voltage of 0.82 V.
■
■
■
■
■
■
■
■
■
■
“Receiver Input Buffer” on page 1–10
“Clock Data Recovery” on page 1–13
“Deserializer” on page 1–14
“Word Aligner” on page 1–15
“Deskew FIFO” on page 1–20
“Rate Match FIFO” on page 1–21
“8B/10B Decoder” on page 1–21
“Byte Deserializer” on page 1–22
“Byte Ordering” on page 1–22
“RX Phase Compensation FIFO” on page 1–23
Table
lists the electrical features supported by the Cyclone IV GX receiver input
1–2:
I/O Standard
Figure 1–3 on page
Programmable Common
Mode Voltage (V)
1–3:
0.82
0.82
0.82
0.82
0.82
Chapter 1: Cyclone IV Transceivers Architecture
Figure
© December 2010 Altera Corporation
1–12. Receiver OCT
Receiver Channel Datapath
AC, DC
Coupling
AC, DC
AC, DC
AC
AC
(1)