EP4CGX150CF23I7N Altera, EP4CGX150CF23I7N Datasheet - Page 90

• Manufacturer Part Number: EP4CGX150CF23I7N
• Description: IC CYCLONE IV FPGA 150K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV GXr

Specifications of EP4CGX150CF23I7N

• Number Of Logic Elements/cells: 149760
• Number Of Labs/clbs: 9360
• Total Ram Bits: 6480000
• Number Of I /o: 270
• Voltage - Supply: 1.16 V ~ 1.24 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 484-FBGA
• Family Name: Cyclone IV
• Number Of Logic Blocks/elements: 149760
• # I/os (max): 270
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 149760
• Ram Bits: 6635520
• Operating Supply Voltage (min): 1.16V
• Operating Supply Voltage (max): 1.24V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

5–28
PLL Control Signals
Clock Switchover
Cyclone IV Device Handbook, Volume 1
f
You can use the pfdena, areset, and locked signals to observe and control the PLL
operation and resynchronization.
For more information about the PLL control signals, refer to the
User
The clock switchover feature allows the PLL to switch between two reference input
clocks. Use this feature for clock redundancy or for a dual-clock domain application,
such as a system that turns on the redundant clock if the previous clock stops running.
Your design can automatically perform clock switchover when the clock is no longer
toggling, or based on the user control signal, clkswitch.
Automatic Clock Switchover
PLLs of Cyclone IV devices support a fully configurable clock switchover capability.
When the current reference clock is not present, the clock-sense block automatically
switches to the backup clock for PLL reference. The clock switchover circuit also sends
out three status signals—clkbad0, clkbad1, and activeclock—from the PLL to
implement a custom switchover circuit. You can select a clock source at the backup
clock by connecting it to the inclk1 port of the PLL in your design.
Figure 5–17
Figure 5–17. Automatic Clock Switchover Circuit
Guide.
inclk1
inclk0
shows the block diagram of the switchover circuit built into the PLL.
muxout
clksw
n Counter
Sense
Clock
Chapter 5: Clock Networks and PLLs in Cyclone IV Devices
refclk
Switchover
Machine
State
© December 2010 Altera Corporation
PFD
ALTPLL Megafunction
clkswitch
(provides manual
switchover support)
fbclk
clkbad0
clkbad1
activeclock
Hardware Features