EP4CGX150CF23I7N Altera, EP4CGX150CF23I7N Datasheet - Page 221

• Manufacturer Part Number: EP4CGX150CF23I7N
• Description: IC CYCLONE IV FPGA 150K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV GXr

Specifications of EP4CGX150CF23I7N

• Number Of Logic Elements/cells: 149760
• Number Of Labs/clbs: 9360
• Total Ram Bits: 6480000
• Number Of I /o: 270
• Voltage - Supply: 1.16 V ~ 1.24 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 484-FBGA
• Family Name: Cyclone IV
• Number Of Logic Blocks/elements: 149760
• # I/os (max): 270
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 149760
• Ram Bits: 6635520
• Operating Supply Voltage (min): 1.16V
• Operating Supply Voltage (max): 1.24V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 8: Configuration and Remote System Upgrades in Cyclone IV Devices
Configuration
© December 2010 Altera Corporation
Figure 8–29. Programming Serial Configuration Devices In-System Using the JTAG Interface
Notes to
(1) Connect the pull-up resistors to the V
(2) The MSEL pin settings vary for different configuration voltage standards and POR time. To connect MSEL for AS
(3) Pin 6 of the header is a V
(4) You must connect the nCE pin to GND or driven low for successful JTAG configuration.
(5) The nCEO pin is left unconnected or used as a user I/O pin when it does not feed the nCE pin of another device.
(6) Power up the V
(7) Connect the series resistor at the near end of the serial configuration device.
(8) These pins are dual-purpose I/O pins. The nCSO pin functions as FLASH_nCE pin in AP mode. The ASDO pin
(9) Resistor value can vary from 1 k to 10 k..
(10) Only Cyclone IV GX devices have an option to select CLKUSR (40 MHz maximum) as the external clock source for
ISP of the Configuration Device
In the second stage, the SFL design in the master device allows you to write the
configuration data for the device chain into the serial configuration device with the
Cyclone IV device JTAG interface. The JTAG interface sends the programming data
for the serial configuration device to the Cyclone IV device first. The Cyclone IV
device then uses the ASMI pins to send the data to the serial configuration device.
Serial Configuration
configuration schemes, refer to
the MSEL pins directly to V
device. For this value, refer to the
ByteBlasterMV download cable, this pin is a no connect. When using USB-Blaster, ByteBlaster II, and EthernetBlaster
cables, this pin is connected to nCE when it is used for AS programming, otherwise it is a no connect.
Third-party programmers must switch to 2.5 V. Pin 4 of the header is a V
The MasterBlaster cable can receive power from either 5.0- or 3.3-V circuit boards, DC power supply, or 5.0 V from
the USB cable. For this value, refer to the
functions as DATA[1] pin in AP and FPP modes.
DCLK.
Device
Figure
DCLK
DATA
ASDI
nCS
8–29:
V
CCIO
CC
10 kΩ
of the EthernetBlaster, ByteBlaster II, USB-Blaster, or ByteBlasterMV cable with a 2.5- V V
(1)
V
25 Ω (7)
CCIO
10 kΩ
(1)
IO
V
CCIO
reference voltage for the MasterBlaster output driver. The V
CCA
10 kΩ
(1)
or GND.
GND
Table 8–3 on page
(2)
N.C. (5)
MasterBlaster Serial/USB Communications Cable User
CCIO
supply of the bank in which the pin resides.
MasterBlaster Serial/USB Communications Cable User
CONF_DONE
nCE (4)
nCEO
nSTATUS
nCONFIG
MSEL[ ]
DATA[0]
DCLK
nCSO (8)
ASDO (8)
Cyclone IV Device
8–8,
Table 8–4 on page
CLKUSR
Loader
Serial
Flash
TDO
TMS
TCK
TDI
CC
(9)
8–8, and
power supply for the MasterBlaster cable.
V
(10)
CCA
Cyclone IV Device Handbook, Volume 1
V
CCA
(9)
Table 8–5 on page
1 kΩ
IO
GND
must match the V
Guide. When using the
Download Cable 10-Pin Male
Pin 1
Header (Top View)
Guide.
GND
8–9. Connect
V
CCA
CCA
CCA
V
IO
supply.
(6)
of the
(3)
8–55
GND