EP4CGX150CF23I7N Altera, EP4CGX150CF23I7N Datasheet - Page 305

• Manufacturer Part Number: EP4CGX150CF23I7N
• Description: IC CYCLONE IV FPGA 150K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV GXr

Specifications of EP4CGX150CF23I7N

• Number Of Logic Elements/cells: 149760
• Number Of Labs/clbs: 9360
• Total Ram Bits: 6480000
• Number Of I /o: 270
• Voltage - Supply: 1.16 V ~ 1.24 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 484-FBGA
• Family Name: Cyclone IV
• Number Of Logic Blocks/elements: 149760
• # I/os (max): 270
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 149760
• Ram Bits: 6635520
• Operating Supply Voltage (min): 1.16V
• Operating Supply Voltage (max): 1.24V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 1: Cyclone IV Transceivers Architecture
Transceiver Clocking Architecture
Table 1–6. REFCLK I/O Standard Support
© December 2010 Altera Corporation
LVDS
LVPECL
1.2 V, 1.5 V,
3.3 V PCML
HCSL
I/O Standard
Protocol
HSSI
PCIe
ALL
ALL
ALL
ALL
ALL
Figure 1–26. PLL Input Reference Clocks in Transceiver Operation for F484 and Larger Packages
Notes to
(1) The REFCLK2 and REFCLK3 pins are dual-purpose CLKIO, REFCLK, or DIFFCLK pins that reside in banks 3A
(2) The REFCLK[1..0] and REFCLK[5..4] pins are dual-purpose differential REFCLK or DIFFCLK pins that
(3) Using any clock input pins other than the designated REFCLK pins as shown here to drive the MPLLs and GPLLs
The input reference clocks reside in banks 3A, 3B, 8A, and 8B have dedicated
V
respective I/O banks to avoid the different power level requirements in the same
bank for general purpose I/Os (GPIOs).
for the REFCLK pins.
(Note
CC_CLKIN3A
and 8A respectively.
reside in banks 3B and 8B respectively. These clock input pins do not have access to the clock control blocks and
GCLK networks. For more details, refer to the
may have reduced jitter performance.
Differential
Differential
AC (Needs
resistor to
Coupling
off-chip
restore
1), (2),
V
Figure
DC
CM
)
, V
1–26:
(3)
CC_CLKIN3B
Termination
Off-chip
Off-chip
Off-chip
Off-chip
Off-chip
Off-chip
Transceiver
Transceiver
MPLL_8
MPLL_7
MPLL_6
MPLL_5
GXBL1
GXBL0
Block
Block
, V
REFCLK[5..4]
CC_CLKIN8A
REFCLK[1..0]
Input
2.5 V
2.5 V
2.5 V
2.5 V
2.5 V
2.5 V
VCC_CLKIN Level
GPLL_2
GPLL_1
, and V
Not applicable in
Clock Networks and PLLs in Cyclone IV Devices
F484 package
REFCLK3
REFCLK2
Table 1–6
Not Supported
Not Supported
Not Supported
Not Supported
Not Supported
Not Supported
CC_CLKIN8B
Output
lists the supported I/O standard
power supplies separately in their
Column I/O
Cyclone IV Device Handbook, Volume 2
Yes
Yes
Yes
Yes
Yes
Yes
Row I/O
I/O Pin Type
No
No
No
No
No
No
chapter.
3A, 3B, 8A, 8B
3A, 3B, 8A, 8B
3A, 3B, 8A, 8B
3A, 3B, 8A, 8B
3A, 3B, 8A, 8B
3A, 3B, 8A, 8B
Supported
Banks
1–25