EP4CGX150CF23I7N Altera, EP4CGX150CF23I7N Datasheet - Page 343

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EP4CGX150CF23I7N

Manufacturer Part Number
EP4CGX150CF23I7N
Description
IC CYCLONE IV FPGA 150K 484FBGA
Manufacturer
Altera
Series
CYCLONE® IV GXr

Specifications of EP4CGX150CF23I7N

Number Of Logic Elements/cells
149760
Number Of Labs/clbs
9360
Total Ram Bits
6480000
Number Of I /o
270
Voltage - Supply
1.16 V ~ 1.24 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
484-FBGA
Family Name
Cyclone IV
Number Of Logic Blocks/elements
149760
# I/os (max)
270
Operating Supply Voltage (typ)
1.2V
Logic Cells
149760
Ram Bits
6635520
Operating Supply Voltage (min)
1.16V
Operating Supply Voltage (max)
1.24V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
484
Package Type
FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant

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Part Number
Manufacturer
Quantity
Price
Part Number:
EP4CGX150CF23I7N
Manufacturer:
Altera
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10 000
Part Number:
EP4CGX150CF23I7N
Manufacturer:
ALTERA
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Chapter 1: Cyclone IV Transceivers Architecture
Transceiver Functional Modes
Figure 1–63. Transceiver Channel Datapath and Clocking when Configured in XAUI Mode
Notes to
(1) Channel 1 low-speed recovered clock.
(2) Low-speed recovered clock.
(3) High-speed recovered clock.
© December 2010 Altera Corporation
Figure 1–63
Fabric
FPGA
coreclkout
:
Figure 1–63
XAUI mode.
/2
Phase
Phase
Phase
Phase
Comp
Comp
Comp
Comp
FIFO
FIFO
FIFO
FIFO
Rx
Rx
Rx
Rx
shows the transceiver channel datapath and clocking when configured in
wr_clk
wr_clk
wr_clk
wr_clk
Tx Phase
Tx Phase
Tx Phase
Tx Phase
Comp
Comp
Comp
Comp
FIFO
FIFO
FIFO
FIFO
rd_clk
rd_clk
rd_clk
rd_clk
Order-
Order-
Order-
Order-
Byte
Byte
Byte
Byte
ing
ing
ing
ing
serializer
serializer
serializer
serializer
/2
/2
/2
/2
Byte
Byte
Byte
Byte
De-
De-
De-
De-
wr_clk
wr_clk
wr_clk
wr_clk
Byte Serializer
Byte Serializer
Byte Serializer
Byte Serializer
/2
/2
/2
/2
Transmitter Channel PCS 3
Transmitter Channel PCS 2
Transmitter Channel PCS 1
Transmitter Channel PCS 0
Receiver Channel PCS 3
Decoder
Receiver Channel PCS 2
Decoder
Receiver Channel PCS 1
Decoder
Receiver Channel PCS 0
Decoder
8B/10B
8B/10B
8B/10B
8B/10B
rd_clk
rd_clk
rd_clk
rd_clk
Match
Match
Match
Match
Rate
FIFO
Rate
FIFO
Rate
FIFO
Rate
FIFO
8B/10B Encoder
8B/10B Encoder
8B/10B Encoder
8B/10B Encoder
(1)
(1)
(1)
(1)
Deskew
Deskew
Deskew
Deskew
FIFO
FIFO
FIFO
FIFO
(2)
(2)
(2)
(2)
Aligner
Aligner
Aligner
Aligner
Word
Word
Word
Word
Cyclone IV Device Handbook, Volume 2
Deserial-
Deserial-
Deserial-
Deserial-
Transmitter Channel PMA 3
Transmitter Channel PMA 2
Transmitter Channel PMA 1
Transmitter Channel PMA 0
Receiver Channel PMA 3
Receiver Channel PMA 2
Receiver Channel PMA 1
Receiver Channel PMA 0
izer
izer
izer
izer
Serializer
Serializer
Serializer
Serializer
(3)
(3)
(3)
(3)
CDR
CDR
CDR
CDR
low-speed clock
high-speed
clock
high-speed
clock
high-speed
clock
high-speed
clock
CDR clock
CDR clock
CDR clock
CDR clock
1–63

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