EP4CGX150CF23I7N Altera, EP4CGX150CF23I7N Datasheet - Page 74

• Manufacturer Part Number: EP4CGX150CF23I7N
• Description: IC CYCLONE IV FPGA 150K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV GXr

Specifications of EP4CGX150CF23I7N

• Number Of Logic Elements/cells: 149760
• Number Of Labs/clbs: 9360
• Total Ram Bits: 6480000
• Number Of I /o: 270
• Voltage - Supply: 1.16 V ~ 1.24 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 484-FBGA
• Family Name: Cyclone IV
• Number Of Logic Blocks/elements: 149760
• # I/os (max): 270
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 149760
• Ram Bits: 6635520
• Operating Supply Voltage (min): 1.16V
• Operating Supply Voltage (max): 1.24V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

5–12
Figure 5–3. Clock Networks and Clock Control Block Locations in EP4CGX30, EP4CGX50, EP4CGX75, EP4CGX110, and
EP4CGX150 Devices
Notes to
(1) The clock networks and clock control block locations in this figure apply to only the EP4CGX30 device in F484 package and all EP4CGX50,
(2) PLL_1, PLL_2, PLL_3, and PLL_4 are general purpose PLLs while PLL_5, PLL_6, PLL_7, and PLL_8 are multipurpose PLLs.
(3) There are 6 clock control blocks on the top, right and bottom sides of the device and 12 clock control blocks on the left side of the device.
(4) REFCLK[0,1]p/n and REFCLK[4,5]p/n can only drive the general purpose PLLs and multipurpose PLLs on the left side of the device.
(5) Not available for EP4CGX30, EP4CGX50, EP4CGX75, EP4CGX110, and EP4CGX150 devices in F484 package.
(6) Dedicated clock pins can feed into this PLL. However, these paths are not fully compensated.
Cyclone IV Device Handbook, Volume 1
EP4CGX75, EP4CGX110, and EP4CGX150 devices.
These clock pins do not have access to the clock control blocks and GCLK networks. The REFCLK[4,5]p/n pins are not available in devices
in F484 package.
PLL_8
PLL_7
PLL_6
PLL_5
REFCLK[0,1]p/n (4)
HSSI
HSSI
(5)
(5)
Figure
REFCLK[4,5]p/n (4)
5–3:
3
(6)
4
(6)
4
(6)
3
(6)
(6)
(Note
PLL_2
PLL_1
(6)
2
2
1),
5
5
Clock
Control
Block (3)
Clock
Control
Block (3)
(2)
4
4
4
4
5
5
GCLK[29..0]
DPCLK[17..15]
DPCLK[2..0]
30
3
CLKIO[15..12]
CLKIO[11..8]
3
Clock
Control
Block (3)
Clock
Control
Block (3)
30
30
4
4
DPCLK[14..12]
DPCLK[5..3]
30
GCLK[29..0]
3
3
Chapter 5: Clock Networks and PLLs in Cyclone IV Devices
4
4
5
5
Clock
Control
Block (3)
(6)
(6)
5
5
© December 2010 Altera Corporation
PLL_4
PLL_3
4
4
3
3
4
Clock Networks
CLKIO[7..4]
DPCLK[11..9]
DPCLK[8..6]