EP4CGX150CF23I7N Altera, EP4CGX150CF23I7N Datasheet - Page 327

• Manufacturer Part Number: EP4CGX150CF23I7N
• Description: IC CYCLONE IV FPGA 150K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV GXr

Specifications of EP4CGX150CF23I7N

• Number Of Logic Elements/cells: 149760
• Number Of Labs/clbs: 9360
• Total Ram Bits: 6480000
• Number Of I /o: 270
• Voltage - Supply: 1.16 V ~ 1.24 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 484-FBGA
• Family Name: Cyclone IV
• Number Of Logic Blocks/elements: 149760
• # I/os (max): 270
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 149760
• Ram Bits: 6635520
• Operating Supply Voltage (min): 1.16V
• Operating Supply Voltage (max): 1.24V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 1: Cyclone IV Transceivers Architecture
Transceiver Functional Modes
© December 2010 Altera Corporation
1
1
SATA
SATA is a computer bus standard that transfers data between the motherboard and
mass storage devices inside and outside the computer. Cyclone IV GX transceiver in
Basic mode supports SATA 1.0 implementation at 1.5 Gbps, and SATA 2.0
implementation at 3.0 Gbps. The following are the options offered in Basic mode that
fulfills SATA protocol implementation:
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■
Clock rate compensation function must be implemented in the user logic as the
receiver rate match FIFO in the PCS compensates up to ±300 PPM between the
upstream transmitter and local receiver clocks. With SSC, the SATA specification
requires clock rate compensation that works up to +350 to -5350 PPM.
V-by-One
V-by-One is a serial interface standard developed to support the higher frame rates
and the higher resolutions required by next-generation flat-panel display.
Cyclone IV GX transceiver in Basic mode supports V-by-One implementation at
3.0 Gbps. Asynchronous SSC with wider spread is supported for receiver in
EP4CGX30 (F484 package), EP4CGX50, and EP4CGX75 devices with CDR in manual
lock mode.
Packer and unpacker, scrambling and descrambling, and clock rate compensation
functions must be implemented in the user logics.
Display Port
Display Port is a digital display interface standard that defines the digital
audio/video interconnect, intended to be used primarily between a computer and its
display monitor, or a computer and a home-theater system. Cyclone IV GX
transceiver in Basic mode supports physical layer implementation of the Display Port
protocol, specification revision of 1.1a. Display Port protocol implementation is
supported in ×1, ×2, and ×4 lanes configuration, at both data rate of 1.62 Gbps and
2.7 Gbps. Asynchronous SSC with wider spread is supported for receiver in
EP4CGX30 (F484 package), EP4CGX50, and EP4CGX75 devices with CDR in manual
lock mode.
Asynchronous SSC support for 0.5% down-spread with 30 kHz - 33 kHz
modulation
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Out-of-Band (OOB) signaling support
■
Supported for receiver in EP4CGX30 (F484 package), EP4CGX50, and
EP4CGX75 devices with CDR in manual lock mode
Supported with putting transmitter in electrical idle state by tri-stating the
output buffer, and receiver signal detection for detecting OOB signals.
Cyclone IV Device Handbook, Volume 2
1–47