EP4CGX150CF23I7N Altera, EP4CGX150CF23I7N Datasheet - Page 403

• Manufacturer Part Number: EP4CGX150CF23I7N
• Description: IC CYCLONE IV FPGA 150K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV GXr

Specifications of EP4CGX150CF23I7N

• Number Of Logic Elements/cells: 149760
• Number Of Labs/clbs: 9360
• Total Ram Bits: 6480000
• Number Of I /o: 270
• Voltage - Supply: 1.16 V ~ 1.24 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 484-FBGA
• Family Name: Cyclone IV
• Number Of Logic Blocks/elements: 149760
• # I/os (max): 270
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 149760
• Ram Bits: 6635520
• Operating Supply Voltage (min): 1.16V
• Operating Supply Voltage (max): 1.24V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 3: Cyclone IV Dynamic Reconfiguration
Dynamic Reconfiguration Modes
Figure 3–4. Write Transaction Waveform—Use ‘logical_channel_address port’ Option
Notes to
(1) In this waveform example, you are writing to only the transmitter portion of the channel.
(2) In this waveform example, the number of channels connected to the dynamic reconfiguration controller is four. Therefore, the
© December 2010 Altera Corporation
logical_channel_address port is 2 bits wide.
logical_channel_address [1:0]
Figure
rx_tx_duplex_sel [1:0]
3–4:
tx_vodctrl [2:0]
Figure 3–4
Read Transaction
For example, to read the existing V
the transmitter portion of a specific channel controlled by the ALTGX_RECONFIG
instance, perform the following steps:
1. Set the logical_channel_address input port to the logical channel address of the
2. Set the rx_tx_duplex_sel port to 2'b10 so that only the transmit PMA controls are
3. Ensure that the busy signal is low before you start a read transaction.
4. Assert the read signal for one reconfig_clk clock cycle. This initiates the read
The busy output status signal is asserted high to indicate that the dynamic
reconfiguration controller is busy reading the PMA control values. When the read
transaction has completed, the busy signal goes low. The data_valid signal is asserted
to indicate that the data available at the read control signal is valid.
reconfig_clk
transceiver channel whose PMA controls you want to read (for example,
tx_vodctrl_out).
read from the transceiver channel.
transaction.
write_all
busy
(2)
(1)
shows the write transaction waveform for Method 1.
3'b111
2'b00
2'b00
OD
values from the transmit V
3'b001
2'b10
2'b01
Cyclone IV Device Handbook, Volume 2
OD
control registers of
3–13