EP4CGX150CF23I7N Altera, EP4CGX150CF23I7N Datasheet - Page 151

• Manufacturer Part Number: EP4CGX150CF23I7N
• Description: IC CYCLONE IV FPGA 150K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV GXr

Specifications of EP4CGX150CF23I7N

• Number Of Logic Elements/cells: 149760
• Number Of Labs/clbs: 9360
• Total Ram Bits: 6480000
• Number Of I /o: 270
• Voltage - Supply: 1.16 V ~ 1.24 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 484-FBGA
• Family Name: Cyclone IV
• Number Of Logic Blocks/elements: 149760
• # I/os (max): 270
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 149760
• Ram Bits: 6635520
• Operating Supply Voltage (min): 1.16V
• Operating Supply Voltage (max): 1.24V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 7: External Memory Interfaces in Cyclone IV Devices
Cyclone IV Devices Memory Interfaces Pin Support
Table 7–1. Cyclone IV GX Device DQS and DQ Bus Mode Support for Each Side of the Device
© December 2010 Altera Corporation
EP4CGX15
EP4CGX22
EP4CGX30
EP4CGX50
EP4CGX75
Device
f
148-pin QFN
169-pin FBGA
169-pin FBGA
324-pin FBGA
484-pin FBGA
484-pin FBGA
672-pin FBGA
All I/O banks in Cyclone IV devices can support DQ and DQS signals with DQ-bus
modes of ×8, ×9, ×16, ×18, ×32, and ×36 except Cyclone IV GX devices that do not
support left I/O bank interface. DDR2 and DDR SDRAM interfaces use ×8 mode DQS
group regardless of the interface width. For a wider interface, you can use multiple ×8
DQ groups to achieve the desired width requirement.
In the ×9, ×18, and ×36 modes, a pair of complementary DQS pins (CQ and CQ#)
drives up to 9, 18, or 36 DQ pins, respectively, in the group, to support one, two, or
four parity bits and the corresponding data bits. The ×9, ×18, and ×36 modes support
the QDR II memory interface. CQ# is the inverted read-clock signal that is connected
to the complementary data strobe (DQS or CQ#) pin. You can use any unused DQ
pins as regular user I/O pins if they are not used as memory interface signals.
For more information about unsupported DQS and DQ groups of the Cyclone IV
transceivers that run at 2.97 Gbps data rate, refer to the
Connection
Table 7–1
Cyclone IV GX device.
Package
(4)
lists the number of DQS or DQ groups supported on each side of the
Guidelines.
Right
Top
Bottom
Right
Top
Bottom
Right
Top
Bottom
Right
Top
Bottom
Right
Top
Bottom
Right
Top
Bottom
Right
Top
Bottom
(2)
(2)
(2)
Side
(3)
(3)
(3)
Number
Groups
×8
1
1
1
1
1
1
1
1
1
2
2
2
4
4
4
4
4
4
4
4
4
Number
Groups
×9
0
0
0
0
0
0
0
0
0
2
2
2
2
2
2
2
2
2
2
2
2
Number
Groups
×16
0
0
0
0
0
0
0
0
0
1
1
1
2
2
2
2
2
2
2
2
2
Cyclone IV Device Family Pin
Cyclone IV Device Handbook, Volume 1
Number
Groups
(Note 1)
×18
0
0
0
0
0
0
0
0
0
1
1
1
2
2
2
2
2
2
2
2
2
Number
(Part 1 of 2)
Groups
×32
—
—
—
—
—
—
—
—
—
—
—
—
1
1
1
1
1
1
1
1
1
Number
Groups
×36
—
—
—
—
—
—
—
—
—
—
—
—
1
1
1
1
1
1
1
1
1
7–3