EP4CGX150CF23I7N Altera, EP4CGX150CF23I7N Datasheet - Page 313

• Manufacturer Part Number: EP4CGX150CF23I7N
• Description: IC CYCLONE IV FPGA 150K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV GXr

Specifications of EP4CGX150CF23I7N

• Number Of Logic Elements/cells: 149760
• Number Of Labs/clbs: 9360
• Total Ram Bits: 6480000
• Number Of I /o: 270
• Voltage - Supply: 1.16 V ~ 1.24 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 484-FBGA
• Family Name: Cyclone IV
• Number Of Logic Blocks/elements: 149760
• # I/os (max): 270
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 149760
• Ram Bits: 6635520
• Operating Supply Voltage (min): 1.16V
• Operating Supply Voltage (max): 1.24V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 1: Cyclone IV Transceivers Architecture
Transceiver Clocking Architecture
© December 2010 Altera Corporation
Bonded Channel Configuration
In bonded channel configuration, the low-speed clock for the bonded channels share a
common bonded clock path that reduces clock skew between the bonded channels.
The phase compensation FIFOs in bonded channels share a set of pointers and control
logic that results in equal FIFO latency between the bonded channels. These features
collectively result in lower channel-to-channel skew when implementing
multi-channel serial interface in bonded channel configuration.
In a transceiver block, the high-speed clock for each bonded channels is distributed
independently from one of the two multipurpose PLLs directly adjacent to the block.
The low-speed clock for bonded channels is distributed from a common bonded clock
path that selects from one of the two multipurpose PLLs directly adjacent to the block.
Transceiver channels for devices in F484 and larger packages support additional
clocking flexibility for ×2 bonded channels. In these packages, the ×2 bonded channels
support high-speed and low-speed bonded clock distribution from PLLs beyond the
two multipurpose PLLs directly adjacent to the block.
low-speed clock sources for the bonded channels.
Table 1–10. High- and Low-Speed Clock Sources for Bonded Channels in Bonded Channel
Configuration
F324 and
smaller
F484 and larger
Note to
(1) GXBL1 is not available for transceivers in F484 package.
Package
Table 1–10
:
GXBL1 (1)
Transceiver
GXBL0
GXBL0
Block
×2 in channels 0, 1
×4 in all channels
×2 in channels 0, 1
×4 in all channels
×2 in channels 0, 1
×4 in all channels
Bonded Channels
High- and Low-Speed Clocks Source
MPLL_5/
MPLL_7/
Table 1–10
MPLL_1
GPLL_1
MPLL_5
MPLL_6
MPLL_7
Option 1
Cyclone IV Device Handbook, Volume 2
lists the high- and
MPLL_2
MPLL_6
MPLL_6
MPLL_8
MPLL_8
Option 2
1–33