EP4CGX150CF23I7N Altera, EP4CGX150CF23I7N Datasheet - Page 116

• Manufacturer Part Number: EP4CGX150CF23I7N
• Description: IC CYCLONE IV FPGA 150K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV GXr

Specifications of EP4CGX150CF23I7N

• Number Of Logic Elements/cells: 149760
• Number Of Labs/clbs: 9360
• Total Ram Bits: 6480000
• Number Of I /o: 270
• Voltage - Supply: 1.16 V ~ 1.24 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 484-FBGA
• Family Name: Cyclone IV
• Number Of Logic Blocks/elements: 149760
• # I/os (max): 270
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 149760
• Ram Bits: 6635520
• Operating Supply Voltage (min): 1.16V
• Operating Supply Voltage (max): 1.24V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

6–8
Table 6–2. Cyclone IV Device I/O Features Support (Part 2 of 2)
Cyclone IV Device Handbook, Volume 1
Differential SSTL-2
Class I (2),
Differential SSTL-2
Class II (2),
Differential SSTL-18
(2),
Differential HSTL-18
(2),
Differential HSTL-15
(2),
Differential HSTL-12
(2),
BLVDS
LVDS
PPDS (3),
RSDS and mini-LVDS
(3),
Differential LVPECL
(5)
Notes to
(1) The default current strength setting in the Quartus II software is 50- OCT without calibration for all non-voltage reference and HSTL/SSTL Class I I/O standards.
(2) The differential SSTL-18 and SSTL-2, differential HSTL-18, HSTL-15, and HSTL-12 I/O standards are supported only on clock input pins and PLL output clock
(3) True differential (PPDS, LVDS, mini-LVDS, and RSDS I/O standards) outputs are supported in row I/O banks 1, 2, 5, and 6 only for Cyclone IV E devices and
(4) This I/O standard is supported for outputs only.
(5) This I/O standard is supported for clock inputs only
(6) The default Quartus II slew rate setting is in bold; 2 for all I/O standards that supports slew rate option.
(7) Differential SSTL-18, differential HSTL-18, HSTL-15, and HSTL-12 I/O standards do not support Class II output.
(8) Cyclone IV GX devices only support right I/O pins.
(7)
(7)
(7)
(7)
(4)
The default setting is 25- OCT without calibration for HSTL/SSTL Class II I/O standards.
pins.
right I/O banks 5 and 6 only for Cyclone IV GX devices. Differential outputs in column I/O banks require an external resistor network.
I/O Standard
(3)
Table
(4)
(7)
(7)
6–2:
1
For more details about the differential I/O standards supported in Cyclone IV I/O
banks, refer to
IOH/IOL Current Strength Setting
Column I/O
8,10,12
8,10,12
8,10,12
8,10,12
8,12,16
8,12
16
—
—
—
—
(mA)
(1)
“High-Speed I/O Interface” on page
Row I/O
8,12,16
8,12
16
—
—
—
—
—
—
—
—
Column
Setting, Ohm ()
I/O
50
25
50
50
50
50
—
—
—
—
—
R
Calibration
S
OCT with
I/O(8)
Row
50
25
—
—
—
—
—
—
—
—
—
Column
Setting, Ohm ()
R
I/O
50
25
50
50
50
50
—
—
—
—
—
S
Calibration
OCT Without
Chapter 6: I/O Features in Cyclone IV Devices
6–23.
I/O(8)
Row
© December 2010 Altera Corporation
50
25
—
—
—
—
—
—
—
—
—
Cyclone
Support
1,2,3,4,
1,2,3,4,
IV E I/O
5,6,7,8
3,4,7,8
5,6,7,8
Banks
IV GX I/O
Cyclone
Support
3,4,5,6,
3,4,5,6,
3,4,5,6,
Banks
4,7,8
7,8
7,8
5,6
7,8
OCT Support
Option
Slew
Rate
0,1,2
0,1,2
(6)
—
—
—
—
Support
clamp
Diode
PCI-
—
—
—
—
—
—
—
—
—
—
—