EP4CGX150CF23I7N Altera, EP4CGX150CF23I7N Datasheet - Page 35

• Manufacturer Part Number: EP4CGX150CF23I7N
• Description: IC CYCLONE IV FPGA 150K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV GXr

Specifications of EP4CGX150CF23I7N

• Number Of Logic Elements/cells: 149760
• Number Of Labs/clbs: 9360
• Total Ram Bits: 6480000
• Number Of I /o: 270
• Voltage - Supply: 1.16 V ~ 1.24 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 484-FBGA
• Family Name: Cyclone IV
• Number Of Logic Blocks/elements: 149760
• # I/os (max): 270
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 149760
• Ram Bits: 6635520
• Operating Supply Voltage (min): 1.16V
• Operating Supply Voltage (max): 1.24V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 2: Logic Elements and Logic Array Blocks in Cyclone IV Devices
Document Revision History
Figure 2–6. Cyclone IV Device LAB-Wide Control Signals
Document Revision History
Table 2–1. Document Revision History
© November 2009 Altera Corporation
November 2009
Date
Dedicated
LAB Row
Clocks
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Figure 2–6
LAB-wide signals control the logic for the clear signal of the register. The LE directly
supports an asynchronous clear function. Each LAB supports up to two asynchronous
clear signals (labclr1 and labclr2).
A LAB-wide asynchronous load signal to control the logic for the preset signal of the
register is not available. The register preset is achieved with a NOT gate push-back
technique. Cyclone IV devices only support either a preset or asynchronous clear
signal.
In addition to the clear port, Cyclone IV devices provide a chip-wide reset pin
(DEV_CLRn) that resets all registers in the device. An option set before compilation in
the Quartus II software controls this pin. This chip-wide reset overrides all other
control signals.
Table 2–1
Version
1.0
shows the revision history for this chapter.
shows the LAB control signal generation circuit.
6
labclk1
Initial release.
labclkena1
labclk2
labclkena2
Changes Made
syncload
labclr1
Cyclone IV Device Handbook, Volume 1
labclr2
synclr
2–7