EP4CGX150CF23I7N Altera, EP4CGX150CF23I7N Datasheet - Page 178

• Manufacturer Part Number: EP4CGX150CF23I7N
• Description: IC CYCLONE IV FPGA 150K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV GXr

Specifications of EP4CGX150CF23I7N

• Number Of Logic Elements/cells: 149760
• Number Of Labs/clbs: 9360
• Total Ram Bits: 6480000
• Number Of I /o: 270
• Voltage - Supply: 1.16 V ~ 1.24 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 484-FBGA
• Family Name: Cyclone IV
• Number Of Logic Blocks/elements: 149760
• # I/os (max): 270
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 149760
• Ram Bits: 6635520
• Operating Supply Voltage (min): 1.16V
• Operating Supply Voltage (max): 1.24V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

8–12
Cyclone IV Device Handbook, Volume 1
1
EPCS1 does not support Cyclone IV devices because of its insufficient memory
capacity.
In configuration mode, the Cyclone IV device enables the serial configuration device
by driving the nCSO output pin low, which connects to the nCS pin of the
configuration device. The Cyclone IV device uses the DCLK and DATA[1]pins to send
operation commands and read address signals to the serial configuration device. The
configuration device provides data on its DATA pin, which connects to the DATA[0]
input of the Cyclone IV device.
All AS configuration pins (DATA[0], DCLK, nCSO, and DATA[1]) have weak internal
pull-up resistors that are always active. After configuration, these pins are set as input
tri-stated and are driven high by the weak internal pull-up resistors.
The timing parameters for AS mode are not listed here because the t
t
PS mode shown in
Multi-Device AS Configuration
You can configure multiple Cyclone IV devices with a single serial configuration
device. When the first device captures all its configuration data from the bitstream, it
drives the nCEO pin low, enabling the next device in the chain. If the last device in the
chain is a Cyclone IV device, you can leave the nCEO pin of the last device
unconnected or use it as a user I/O pin after configuration. The nCONFIG, nSTATUS,
CONF_DONE, DCLK, and DATA[0] pins of each device in the chain are connected
together
STATUS
, t
CF2ST1
(Figure
, and t
8–3).
CD2UM
Table 8–10 on page
timing parameters are identical to the timing parameters for
Chapter 8: Configuration and Remote System Upgrades in Cyclone IV Devices
8–35.
© December 2010 Altera Corporation
CF2CD
, t
CF2ST0
Configuration
, t
CFG
,