EP4CGX150CF23I7N Altera, EP4CGX150CF23I7N Datasheet - Page 141

• Manufacturer Part Number: EP4CGX150CF23I7N
• Description: IC CYCLONE IV FPGA 150K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV GXr

Specifications of EP4CGX150CF23I7N

• Number Of Logic Elements/cells: 149760
• Number Of Labs/clbs: 9360
• Total Ram Bits: 6480000
• Number Of I /o: 270
• Voltage - Supply: 1.16 V ~ 1.24 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 484-FBGA
• Family Name: Cyclone IV
• Number Of Logic Blocks/elements: 149760
• # I/os (max): 270
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 149760
• Ram Bits: 6635520
• Operating Supply Voltage (min): 1.16V
• Operating Supply Voltage (max): 1.24V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 6: I/O Features in Cyclone IV Devices
High-Speed I/O Standards Support
LVPECL I/O Support in Cyclone IV Devices
© December 2010 Altera Corporation
f
Figure 6–17
bottom I/O banks.
Figure 6–17. RSDS Interface with Single Resistor Network on the Top and Bottom I/O Banks
Note to
(1) R
The LVPECL I/O standard is a differential interface standard that requires a 2.5-V
V
telecommunications, data communications, and clock distribution. Cyclone IV
devices support the LVPECL input standard at the dedicated clock input pins only.
The LVPECL receiver requires an external 100- termination resistor between the two
signals at the input buffer.
For the LVPECL I/O standard electrical specification, refer to the
Datasheet
AC coupling is required when the LVPECL common mode voltage of the output
buffer is higher than the Cyclone IV devices LVPECL input common mode voltage.
Figure 6–18
receiver are external to the device. DC-coupled LVPECL is supported if the LVPECL
output common mode voltage is in the Cyclone IV devices LVPECL input buffer
specification (refer to
(Note 1)
CCIO.
P
This standard is used in applications involving video graphics,
value is pending characterization.
Figure
RSDS Transmitter
chapter.
Cyclone IV Device
6–17:
Emulated
shows the RSDS interface with a single resistor network on the top and
shows the AC-coupled termination scheme. The 50- resistors used at the
Figure
Single Resistor Network
6–19).
R
P
50 Ω
50 Ω
100 Ω
Cyclone IV Device Handbook, Volume 1
Cyclone IV Device
RSDS Receiver
6–33